68HC705BD7 datasheet(67/85 Pages) FREESCALE

67 / 85 page

SECTION 11: MULTI-FUNCTION TIMER

Page 57

MC68HC05BD7 Rev. 2.0

GENERAL RELEASE SPECIFICATION

SECTION 11

MULTI-FUNCTION TIMER

11.1

Introduction

This module provides miscellaneous function to the MC68HC05BD7. It includes a timer

overflow, real-time interrupt, and watchdog functions. Also included in the module is the

capability of selecting the mode of the maskable external interrupt pin, either edge-

triggered mode only or both edge-triggered mode and level-triggered mode.

The clock base for this module is derived from bus clock divided by four. For a 2 MHz E

(CPU) clock, the clock base is 0.5 MHz. This clock base is then divided by an 8-stage ripple

counter to generate the timer overflow. Timer overflow rate is thus E/1024. The output of

this 8-stage ripple counter then drives one stage divider to generate real time interrupt.

Hence, the clock base for real time interrupt is E/2,048. Real time interrupt rate is selected

by RT0 and RT1 bits of Multi-Function Timer Control/Status Register (MFTCSR). The

interrupt rates are E/2,048, E/(2,048X2), E/(2,048X4), and E/(2,048X8). The selected real

time interrupt rate is then divided by 64 to generate COP reset.

The COP watchdog timer function is implemented by using a COP counter. The minimum

COP reset rates are controlled by RT0 and RT1 of MFTCSR. If the COP circuit times out,

an internal reset is generated and the normal reset vector is fetched. Preventing a COP

time-out is done by writing a ‘0’ to bit 0 of address $3FF0. This write operation resets the

divide-by-64 counter stage described in the previous paragraph. The COP counter has to

be cleared periodically by software with a period less than COP reset rate. It continues to

count even though the CPU is in WAIT mode. In MC68HC05BD7, the COP is always

enabled.

11.2

There are two registers in the Multi-Function Timer as discussed below.

11.2.1

Multi-function Timer Control/status Register

NOTE:

Please don’t use BSET or BCLR to manipulate this register when I-bit is

clear, or it will generate abnormal reset.

TOF

bit 7

Timer Overflow Flag indicates if the 8-bit ripple counter

overflows. TOF is set when the 8-bit counter rolls over from

0000011

6543210

MFTCSR

$0008

reset

⇒

TOF

RTIF

TOFIE

RTIE

IRQN

RT1

RT0

INHIRQ

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

68HC705BD7 Datasheet(PDF) 67 Page - Freescale Semiconductor, Inc

68HC705BD7 Datasheet(HTML) 67 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85

Datasheet Download

Link URL