68HC705BD7 datasheet(19/85 Pages) FREESCALE

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SECTION 1: GENERAL DESCRIPTION

Page 9

MC68HC05BD7 Rev. 2.0

GENERAL RELEASE SPECIFICATION

1.2.12

PWM0**-PWM7**

These pins are dedicated for 8-bit PWM channels 0 to 7, which have +5V open-drain

software options. See SECTION 8 for a detailed description.

1.2.13

HSYNC, VSYNC

These two input pins are for video sync signals input from the host computer. The signals

will be used for video mode detection and output to HSYNO and VSYNO. The host

computer can also send a composite sync signal to the HSYNC input. This composite

signal will be separated internally. The polarity of the input signals can be either positive or

negative. These two pins contain internal Schmitt triggers as part of their inputs to improve

noise immunity. See SECTION 10 for a detail description.

1.3

Options

MC68HC05BD7 provides an option for IRQ interrupt edge only sensitivity or edge and level

sensitivity and one option register for individual PWM channels 0 to 7 to be programmed

as open-drain type output. The IRQ option is selected by setting the appropriate bit in the

MFTCSR register at address $0008 and the PWM open-drain option register is located at

address $0012.

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68HC705BD7 Datasheet(PDF) 19 Page - Freescale Semiconductor, Inc