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68HC705BD7 Datasheet(PDF) 45 Page - Freescale Semiconductor, Inc |
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68HC705BD7 Datasheet(HTML) 45 Page - Freescale Semiconductor, Inc |
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45 / 85 page ![]() SECTION 7: INPUT/OUTPUT PORTS Page 35 MC68HC05BD7 Rev. 2.0 GENERAL RELEASE SPECIFICATION Table 7-1: I/O Pin Functions NOTE: A “glitch” can be generated on an I/O pin when changing it from an input to an output unless the data register is first pre-conditioned to the desired state before changing the corresponding DDR bit from a zero to a one. 7.6 Port C and D Configuration Register Port C and Port D are shared with PWM, ADC, DDC12AB, and SYNC Processor. The configuration registers at $0A and $0B are used to configure those I/O pins. They are default to zero after poWer-on reset. Setting these bits will set the corresponding pins to the corresponding functions. For example, setting SCL and SDA bits of register $0B will configure Port D pins 1 and 0 as DDC12AB pins, regardless of DDR1 and DDR0 settings. When any PWM8-PWM15 bits of CR1 register are set, the corresponding pins of port C become the PWM output if the corresponding bits in CR2 register are clear. When the pin is defined as PWM channel, it become an output only pin. When any ADC3-ADC0 bits of the CR2 register are set, the corresponding pins of port C become the ADC input channels. When HSYNO or VSYNO is set, the PC2 or PC3 becomes the output of HSYNC or VSYNC accordingly, see SECTION 10 for the detail description of HSYNO and VSYNO outputs. When SCL and SDA bits of the CR2 register are set, the DDC12AB use these two pins as clock and data pins. In summary, the configuration in the CR2 register has higher priority than in the CR1 register. R/W DDR I/O Pin Functions 0 0 The I/O pin is in input mode. Data is written into the output data latch. 0 1 Data is written into the output data latch and output to the I/O pin. 1 0 The state of the I/O pin is read. 1 1 The I/O pin is in output mode. The output data latch is read. W R CR1 $000A reset ⇒ PWM15 0 7 00 54 0 0000 6 3210 PWM14 PWM11 PWM10 PWM9 PWM8 PWM13 PWM12 W R CR2 $000B reset ⇒ 0 7 00 54 0 0000 6 3210 ADC2 SCL SDA ADC1 ADC0 HSYNO VSYNO ADC3 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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