68HC705BD7 datasheet(78/85 Pages) FREESCALE

78 / 85 page

SECTION 13: ELECTRICAL SPECIFICATIONS

Page 68

GENERAL RELEASE SPECIFICATION

MC68HC05BD7 Rev. 2.0

13.5

DDC12AB TIMING

(VDD = 5.0 Vdc ±10%, VSS = 0Vdc, TA = 0˚C to +70˚C, unless otherwise noted

13.5.1

DDC12AB Interface Input Signal Timing

13.5.2

DDC12AB Interface Output Signal Timing

NOTE:

1. With 200 pF loading on the SDA/SCL pins

Parameter

Symbol

Min

Max

Units

START condition hold time

tHD.STA

2—

tCYC

Clock low period

tLOW

4—

tCYC

Clock high period

tHIGH

4—

tCYC

Data set up time

tSU.DAT

250

—

Data hold time

tHD.DAT

0—

START condition set up time (for repeated START condition only)

tSU.STA

2—

tCYC

STOP condition set up time

tSU.STO

2—

tCYC

Parameter

Symbol

Min

Max

Units

SDA / SCL rise time (see NOTE 1)

—

1.0

µs

SDA / SCL fall time (see NOTE 1)

—

300

Data set up time

tSU.DAT

tLOW

—ns

Data hold time

tHD.DAT

0—

tHD.STA

tLOW

tHIGH

tSU.DAT

tHD.DAT

tSU.STO

SDA

SCL

tSU.STA

Freescale Semiconductor, Inc.

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