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68HC705BD7 Datasheet(PDF) 60 Page - Freescale Semiconductor, Inc |
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68HC705BD7 Datasheet(HTML) 60 Page - Freescale Semiconductor, Inc |
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60 / 85 page  SECTION 10: SYNC PROCESSOR Page 50 GENERAL RELEASE SPECIFICATION MC68HC05BD7 Rev. 2.0 corresponding polarity control bits, bit 3 and bit 2 of register $0C, can change the polarity of HSYNO/VSYNO outputs. The result HSYNO and VSYNO outputs can vary while the setting in SPCSR and SPIOCR register is different. If the COMP bit in SPCSR register is set, the incoming composite Sync signal will be the HSYNO output and the extracted VSYNC with 6~7us delay will be the VSYNC output. When the SOUT bit in SPIOCR register is set, the internal free-running 55.556KHz with 2us pulse will be the HSYNO output and the other free-running 72.34Hz with 108us pulse will be the VSYNO output. 10.2.4 CLAMP Pulse Output The logic will generate a 0.5us - 0.75us pulse at either the leading edge or the trailing edge which is specified by the BPOR bit in the SPIOCR register. See Figure 10-1 for its detail timing relation. One control bit to invert the output polarity of CLAMP pulse is located at bit 5 of SPIOCR. Figure 10-1: CLAMP output waveform HSYNC (HPOL=1) CLAMP (BPOR=0) CLAMP (BPOR=1) HSYNC (HPOL=0) CLAMP (BPOR=0) CLAMP (BPOR=1) 0.5-0.75us 0.5-0.75us 0.5-0.75us 0.5-0.75us 0.5-0.75us 0.5-0.75us 0.5-0.75us Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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