68HC705BD7 datasheet(48/85 Pages) FREESCALE

48 / 85 page

SECTION 8: PULSE WIDTH MODULATION

Page 38

GENERAL RELEASE SPECIFICATION

MC68HC05BD7 Rev. 2.0

Figure 8-2: Relationship Between 5-Bit PWM and 3-Bit BRM

8.2

Open-Drain Option Register

This PWM Open-Drain option Register contains 8 bits which are programmed to change

the output drive of individual PWM channel from channel 0 to channel 7 to be open-drain

type. This register is located at $0012

Figure 8-3: PWM Open-Drain Option Register

When any bit in this register is one, the corresponding PWM channel output becomes +5V

open-drain type. When the bit is zero, the corresponding PWM channel has push-pull

output. All eight bits are clear upon reset.

32 T

M = $00

M = $01

M = $0F

M = $1F

Narrow pulse possibly inserted

by the BRM

T = 1 MCU Clock Period (0.5

µs if MCU clock = 2 MHz)

PWM cycles in which narrow pulses are

inserted in an 8-cycle frame

2, 6

1, 3, 5, 7

XX1

X1X

1XX

6PWMO

4PWMO

7PWMO

1PWMO

2PWMO

3PWMO

0000000

6543210

5PWMO

PWMOR

$12

reset

⇒

0PWMO

Freescale Semiconductor, Inc.

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