68HC705BD7 datasheet(14/85 Pages) FREESCALE

14 / 85 page

SECTION 1: GENERAL DESCRIPTION

Page 4

GENERAL RELEASE SPECIFICATION

MC68HC05BD7 Rev. 2.0

Figure 1-1: MC68HC05BD7 Block Diagram

PB0

PB1

PB2*

PB3*

PB4*

PB5*

OSCILLATOR

AND DIVIDE

BY 2

DATA

DIR

REG

PORT

REG

EXTAL XTAL

CORE

TIMER

(COP)

RAM

256 bytes for HC05BD2

384 bytes for HC05BD7

384 bytes for HC705BD7

5.75K-bytes ROM for

HC05BD2

11.75K-bytes ROM

for HC05BD7

11.5K-bytes EPROM

for HC705BD7

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

DATA

DIR

REG

PORT

REG

PC0*/PWM8*

PC1*/PWM9*

PC2/PWM10/ADC0

PC3/PWM11/ADC1

PC4/PWM12/ADC2

PC5/PWM13/ADC3

PC6/PWM14/VSYNO

PC7/PWM15/HSYNO

DATA

DIR

REG

PORT

REG

RESET IRQ/VPP

Pulse

Width

Modulation

(PWM)

SYNC

PROCESSOR

HSYNC

VSYNC

VDD

VSS

STK PTR

COND CODE REG 1 1 1

I N Z C

INDEX REG

CPU CONTROL

0 0 0

ALU

68HC05 CPU

ACCUM

PROGRAM COUNTER

CPU REGISTERS

DDC12AB

PWM0**

PWM1**

PWM2**

PWM3**

PWM4**

PWM5**

PWM6**

PWM7**

PORT

REG

DATA

DIR

REG

PD1*/SCL*

PD0*/SDA*

*: +12V open-drain

PD3*/SOG

PD2***/CLAMP

6-bit ADC

**: +5V open-drain option

***: +5V open-drain

IRQ/VPP: VPP valid for HC705 version only, not used for HC05 version

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

68HC705BD7 Datasheet(PDF) 14 Page - Freescale Semiconductor, Inc

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