68HC705BD7 datasheet(5/85 Pages) FREESCALE

5 / 85 page

Page iii

MC68HC05BD7 Rev. 2.0

GENERAL RELEASE SPECIFICATION

9.3.6

DDC Data Receive Register (DDRR)..................................44

9.4

Data Sequence .........................................................................45

9.5

Program Algorithm....................................................................45

SECTION 10

SYNC PROCESSOR...................................................... 49

10.1

Introduction ...............................................................................49

10.2

Functional Blocks......................................................................49

10.2.1

Polarity Detection ................................................................49

10.2.2

Sync Signal Counters..........................................................49

10.2.3

Polarity Controlled HSYNO/VSYNO Outputs ......................49

10.2.4

CLAMP Pulse Output ..........................................................50

10.3

Registers...................................................................................51

10.3.1

Sync Processor Control and Status Register (SPCSR) ......51

10.3.2

Sync Processor Input/Output Control Register (SPIOCR) ..52

10.3.3

Vertical Frequency Registers (VFRs)..................................53

10.3.4

Hsync Frequency Registers (HFRs)....................................54

10.4

System Operation .....................................................................54

SECTION 11

MULTI-FUNCTION TIMER............................................. 57

11.1

Introduction ...............................................................................57

11.2

11.2.1

Multi-function Timer Control/status Register .......................57

11.2.2

MFT Timer Counter Register...............................................59

SECTION 12

A/D CONVERTER.......................................................... 61

12.1

Introduction ...............................................................................61

12.2

Input..........................................................................................61

12.2.1

ADC0-ADC3 ........................................................................61

12.3

Registers...................................................................................62

12.3.1

ADC Control/status Register ...............................................62

12.3.2

ADC Channel Register ........................................................62

12.4

Program Example .....................................................................63

SECTION 13

ELECTRICAL SPECIFICATIONS.................................. 65

13.1

Maximum Ratings .....................................................................65

13.2

Thermal Characteristics............................................................65

13.3

DC Electrical Characteristics ....................................................66

13.4

Control Timing ..........................................................................67

13.5

DDC12AB TIMING....................................................................68

13.5.1

DDC12AB Interface Input Signal Timing .............................68

13.5.2

DDC12AB Interface Output Signal Timing ..........................68

13.6

HSYNC/VSYNC Input Timing ...................................................69

SECTION 14

MECHANICAL SPECIFICATIONS ................................ 71

14.1

Introduction ...............................................................................71

14.2

40-Pin DIP Package (Case 711-03) .........................................71

14.3

42-Pin SDIP Package (Case 858-01) .......................................71

Freescale Semiconductor, Inc.

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