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OR3LP26B Datasheet(PDF) 124 Page - Agere Systems |
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OR3LP26B Datasheet(HTML) 124 Page - Agere Systems |
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124 / 184 page  ORCA OR3LP26B FPSC Data Sheet Embedded Master/Target PCI Interface March 2000 124 Lucent Technologies Inc. Lucent Technologies Inc. Configuration Space of the PCI Core (continued) Table 42. Configuration Space Assignment * These values are intended to be custom assigned, per the intended application, by assigning constants via the FPGA configuration bit stream. † These exhibit special behavior per the PCI Specification: — Reads behave normally. — Writing a 1 clears the bit to zero. — Writing a 0 has no effect on the bit. ‡ This bit is set when the device detects any type of parity error from its own master or target. § Bytes 10—27 hex contain the base address registers (BARs). — Any legal combination of memory and I/O BARs is permitted, as long as 64-bit BARs are naturally aligned, that is, they occupy bytes 10—17, 18—1F, or 20—27 hex. — Memory BARs may be marked as prefetchable/nonprefetchable by setting/resetting bit 3; however, the PCI core’s behavior is not affected by this setting. In particular, the Target read operation may discard unused FIFO read-ahead data even though the data space is marked as nonprefetchable (this is not a violation, since the nonprefetchable bit only says that data can’t be discarded once it has been sent over the PCI bus; nevertheless, caution must be exercised when this bit is reset). Bytes Width Bit Description Read/Write Initial Value 00—01 16 — Vendor ID Read Only 11C1h (Lucent) 02—03 16 — Device ID Read Only 5401h (OR3LP26B) 04—05 16 0 1 2 3 4 5 6 7 8 9 15—10 Command: Enable I/O Space Enable Memory Space Enable Bus Master Enable Special Cycle Enable Mem Wr & Inv Enable VGA Palette Snoop Enable Par Err Response Enable Stepping Enable SERRn Enable Fast Back-to-Back Reserved Read/Write Read/Write Read/Write Read Only Read/Write Read Only Read/Write Read Only Read/Write Read/Write Read Only 0 0 * 0 0 0 0 0 0 0 zeros 06—07 16 4—0 5 6 7 8 10—9 11 12 13 14 15 Status: Reserved 66 MHz Capable UDF Supported Fast Back-to-Back Data PERRn Detected devseln Timing Target Abort Signaled Target Abort Received Master Abort Received System Error Signaled Parity Error Detected Read Only Read Only Read Only Read Only † Read Only † † † † † ‡ zeros 1 0 1 0 01b (medium) 0 0 0 0 0 08 8 — Revision ID Read Only * 09—0B 24 — Class Code Read Only * 0C 8 — Cache Line Size Read Only zeros 0D 8 7—3 2—0 Latency Timer: Programmable Portion Granularity = 8 clks Read/Write Read Only zeros zeros 0E 8 — Header Type Read Only 00h 0F 8 — BIST Read Only zeros 10—27 192 — BAR § * 28—2B 32 — Cardbus CIS Pointer Read Only zeros 2C—2D 16 — Subsystem Vendor ID Read Only zeros 2E—2F 16 — Subsystem ID Read Only * 30—33 32 — Expansion ROM Base Address Read Only zeros 34 8 — (Capabilities Pointer) — 50h 35—37 24 — (Reserved) Read Only zeros 38—3B 32 — (Reserved) Read Only zeros |
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