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OR3LP26B Datasheet(PDF) 125 Page - Agere Systems |
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OR3LP26B Datasheet(HTML) 125 Page - Agere Systems |
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125 / 184 page  Lucent Technologies Inc. 125 Data Sheet ORCA OR3LP26B FPSC March 2000 Embedded Master/Target PCI Interface Lucent Technologies Inc. Configuration Space of the PCI Core (continued) Table 42. Configuration Space Assignment (continued) * These values are intended to be custom assigned, per the intended application, by assigning constants via the FPGA configuration bit stream. † These exhibit special behavior per the PCI Specification: — Reads behave normally. — Writing a 1 clears the bit to zero. — Writing a 0 has no effect on the bit. ‡ This bit is set when the device detects any type of parity error from its own master or target. § Bytes 10—27 hex contain the base address registers (BARs). — Any legal combination of memory and I/O BARs is permitted, as long as 64-bit BARs are naturally aligned, that is, they occupy bytes 10—17, 18—1F, or 20—27 hex. — Memory BARs may be marked as prefetchable/nonprefetchable by setting/resetting bit 3; however, the PCI core’s behavior is not affected by this setting. In particular, the Target read operation may discard unused FIFO read-ahead data even though the data space is marked as nonprefetchable (this is not a violation, since the nonprefetchable bit only says that data can’t be discarded once it has been sent over the PCI bus; nevertheless, caution must be exercised when this bit is reset). ** These signals are tied to the FPGA signal of the same name and are not initialized. †† This 32-bit register is used during manufacturing test. Writes are not allowed; reads are allowed and cause no side effects, but the value returned is undefined. ‡‡ These exhibit special behavior per the CompactPCI Hot Swap Specification: — Reads behave normally. — Writing a 1 clears the bit to zero. — Writing a 0 has no effect on the bit. Bytes Width Bit Description Read/Write Initial Value 3C 9 — Interrupt Line Read/Write zeros 3D 8 — Interrupt Pin Read Only 01h (INTAn) 3E 8 — Min_Gnt Read Only * 3F 8 — Max_Lat Read Only * 40—41 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FPGA Config. Command-Status Register: Gsr PCI Core Global Set/Reset ConfigFPGA Enable FPGA Config. RdCfgN Enable Readback PrgmN Reset FPGA Config. Logic FastSlowN Fast/Slow Config. Clock BitErr_1 Error Signal from FPGA BitErr_0 Error Signal from FPGA CfgBusy Cfg Not In Idle State RdBkNext Readback Handshake PciRegVld Configuration Handshake SRFull Shift Reg Full SREmpty Shift Reg Empty HndShkErr Handshake Error InitN FPGA’s INITN Done FPGA’s DONE Mode PCI Core Mode Read/Write Read/Write Read/Write Read/Write Read/Write Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read/Write Read Only Read Only Read Only 0 0 1 1 0 0 0 0 0 0 0 0 0 ** ** 0 42—43 16 (Reserved) Read Only zeros 44—47 32 FPGA Config. Data Register Read/Write zeros 48-4B 32 Scratch Register Read/Write zeros 4C 32 Reserved for Manufacturing Testing †† Footnote 7 50 8 Capability ID Read Only 06h (Hot Plug) 51 8 Next Item Read Only 00h (Last item) 52 7 6 5 4 3 2 1 0 Hot Swap Control Status Register: INS ENUMn Status - Insertion EXT ENUMn Status - Extraction Reserved Reserved LOO Reserved EIM ENUMn Signal Mark Reserved ‡‡ ‡‡ Read Only Read Only Read/Write Read Only Read/Write Read Only 1 0 0 0 0 0 0 0 |
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