OR3LP26B datasheet(126/184 Pages) AGERE

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Lucent Technologies Inc.

ORCA OR3LP26B FPSC

Data Sheet

Embedded Master/Target PCI Interface

March 2000

Lucent Technologies Inc.

FPSC Configuration

The OR3LP26B FPSC provides the designer many

configuration options. In addition to all the configuration

options provided in the standard Series 3 architecture

(except Master parallel mode) including configuration

via the microprocessor and boundary-scan (JTAG)

interfaces, the OR3LP26B PCI FPSC also allows con-

figuration via the PCI interface. With this capability,

many configuration schemes can be implemented. For

example, a generic FPSC configuration can be loaded

via a serial configuration PROM and updated via the

PCI bus or the microprocessor interface. The FPSC

can also be reprogrammed in the field, or the configu-

ration can be dynamically modified to perform different

tasks.

When the FPSC is configured via the PCI interface,

there is a priority issue that must be resolved. The Sub-

system vendor ID and subsystem ID that reside at

2Ch—2Fh in the PCI configuration space can be

assigned during FPGA configuration, but these same

pieces of information may be needed by system soft-

ware to determine which FPSC configuration bit stream

to use for each FPSC when two or more FPSCs reside

on one PCI bus. For this reason, the OR3LP26B FPSC

is designed to allow for two different configuration

schemes.

The first option is more flexible; in this scheme, the

FPSC is first configured without employing the PCI

interface (e.g., via serial PROM). The access to the

FPSC's configuration registers via the PCI interface

occurs after this first configuration completes, so that

when the subsystem vendor ID and subsystem ID are

finally read, they properly and uniquely identify the card

on which the FPSC resides. This initial configuration bit

stream is only required to provide correct subsystem

vendor ID and subsystem ID values for system soft-

ware use, but it may in addition be the first version of

the FPSC's application code. The PCI system software

is then able to invoke the proper procedures that will

reconfigure the FPSC using the desired version of the

configuration bit stream.

The disadvantage of the first option is that it requires

that the FPSC be preconfigured prior to receiving the

working bit stream via the PCI interface. In a propri-

etary system, however, a second option may be

employed if the configuring software may already know

which bit stream to use to configure the FPSC. The

system software can simply locate the OR3LP26B by

reading the vendor ID and device ID, and then proceed

directly to FPSC configuration via the PCI bus. This

feature takes advantage of the fact that the PCI inter-

face is functional even before the FPSC has been con-

figured.

Configuration via PCI Bus

The OR3LP26B is configured using locations 40 hex

through 47 hex. These registers are dedicated to the

FPSC configuration and readback functions, as

detailed in Tables 36 and 37. The FPGA configuration

control-status register (FCCSR) is a 16-bit register at

address 40 hex—41 hex, and the FPGA configuration

data register (FCDR) is a 32-bit register at address

44 hex—47 hex.

The following is an example sequence which config-

ures the FPSC via the PCI interface:

1. Read the vendor ID and device ID registers. If the

vendor ID is 11C1 hex, the vendor, or chip manufac-

turer, is Lucent. If, in addition, the device ID is

5401 hex, the device is a Lucent OR3LP26B PCI

FPSC; go to step 2.

2. At this point, the configuration software may do one

of two things. If this is a proprietary system and the

configuration software already knows how to config-

ure any Lucent OR3LP26B, the software may skip

the next two steps, and the FPSC does not need to

be preconfigured. If this is a standard system, the

configuration software must perform the next two

steps to uniquely identify the application that is uti-

lizing the OR3LP26B.

3. Read the FCCSR [1] until Done goes active-high,

signaling that the FPSC preconfiguration operation

has completed, typically via a serial configuration

PROM.

4. Read the class code, revision ID, subsystem vendor

ID, and subsystem ID registers. This information is

programmed into the FPSC by the preconfiguration

step. This information is used by the configuration

software to locate the correct FPSC configuration

bit stream and driver for the FPSC's application,

and is provided by the manufacturer of the adapter

card containing the FPSC.

5. Read the FCCSR until bit 0 goes high. If communi-

cation with the FPSC is underway via the boundary-

scan hardware, this signal will remain inactive-low

until it completes.

6. Write to the FCCSR three times, first with PrgmN

high, then low, then high.

7. Write to the FCCSR with ConfigFPGA high. This will

initiate an FPSC configuration session via the PCI

interface.

8. Wait for the RAM initialization to complete by moni-

toring FCCSR [2]. Wait for 1.5 ms, and then send

one word of all ones. If InitN is high, continue with

real data; otherwise, repeat or declare the problem.

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