OR3LP26B datasheet(128/184 Pages) AGERE

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Lucent Technologies Inc.

ORCA OR3LP26B FPSC

Data Sheet

Embedded Master/Target PCI Interface

March 2000

Lucent Technologies Inc.

Clocking Options at FPGA/Core

Boundary

The OR3LP26B supports a wide variety of integrated

FPGA/core clocking schemes which, in conjunction

with the FIFO interfaces between the PCI bus and the

FPGA, gives the designer many flexible options.

The Master and Target FIFOs are independently

clocked on the FPGA side by either fclk1 or fclk2. The

clocks used for the Master FIFO and Target FIFO inter-

faces to the FPGA logic are independent when the

interface is configured in quad-port mode, but they

must be tied to the same clock signal for dual-port

mode.

Figure 48 illustrates the special clock paths provided to

service the clocking needs of PCI functions. The vari-

ous clocking options shown in Figure 48 are discussed

below.

Although there are many clocking options, minimum

clock skew is obtained by following the following recom-

mendations. This section is divided into internally gen-

erated clocks, external system clocks, external express

clocks, and external corner clocks that utilize the PLLs.

Refer to the Series 3L data sheet and application notes

for a full description of all of the clocking options avail-

able for the Series 3L parts.

PCI Clock as System Clock

The clock received from the PCI interface can be

brought across the PCI core into the FPGA logic sec-

tion and used as the clock for the entire FPSC, or even

as the clock for the entire board on which the FPSC

resides. It is important that this signal be available via

the PCI core since PCI rules allow for only one load per

agent on the PCI bus clock. The FPSC incorporates

special clock lines for the purpose of distributing the

PCI clock; these lines are hard-connected to the PCI

core's circuitry but can also be passed up onto the

FPGA portion's clock grid. From there, in addition to

feeding clocks to all PFUs and PIOs, this clock can also

drive the clock inputs to the FPGA side of the Master

and/or Target FIFOs, and can be made available off-

chip.

Local Clock as System Clock

The FIFO-buffered interface between the PCI logic and

the FPGA allows other clocks to be utilized in the

FPGA as well. The Master and Target interfaces each

have independent clock nets and can be connected to

the same or separate clocks. Essentially, this means

that both the Master and Target logic and FIFOs can be

independently set to use the PCI clock or another

clock. Clocks can be fed from any I/O pad, from

express clock inputs, or from internal logic, and can be

fed via the programmable clock manager (PCM).

Internally Generated Clocks

There are no limitations for using 1 or 2 internally

generated clocks to connect to the fclk1 and/or fclk2

clock input pins.

External System Clocks

External system clocks are clock inputs that do not use

the three dedicated eclk input clock pins of the device.

Keep the clocks toward the center of a side instead

of in the corners for minimal skew across the FPGA.

The best skew across the FPGA/ASIC boundary is

obtained by selecting pins on the left or right side of

the die. Avoid using general I/O as clock inputs on

the top of the device.

Refer to the Series 3 clocking application note for

general FPGA clocking rules.

External Express Clocks

External express clocks are externally generated

clocks that enter on one of the three eclk pins of the

device.

The best skew across the FPGA/ASIC boundary is

obtained by selecting the eclk pin on the right side of

the device (eclkr). Avoid using the top or left side

eclk inputs.

Externally Generated Clocks Entering Through

PCM Input Pins

External PCM clocks are clocks entering and going

through the programmable clock managers.

When using a programmable clock manager, either

the upper right or lower left clock managers may be

used.

Clock Sourced from pciclk

There are no limitations for using the pciclk clock

output to connect to the fclk1 and/or fclk2 clock

input pins.

OR3LP26B Datasheet(PDF) 128 Page - Agere Systems

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