S25FS256S datasheet(128/154 Pages) SPANSION

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S25FS-S Family

S25FS-S_00_04 November 6, 2013

Data

Sheet

(Pre limin ar y)

10.8.7

PPB Erase (PPBE E4h)

The PPB Erase (PPBE) command sets all PPB bits to 1. Before the PPB Erase command can be accepted by

the device, a Write Enable (WREN) command must be issued and decoded by the device, which sets the

Write Enable Latch (WEL) in the Status Register to enable any write operations.

The instruction E4h is shifted into SI by the rising edges of the SCK signal.

CS# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on

SI. This will initiate the beginning of internal erase cycle, which involves the pre-programming and erase of

the entire PPB memory array. Without CS# being driven to the logic high state after the eighth bit of the

instruction, the PPB erase operation will not be executed.

With the internal erase cycle in progress, the user can read the value of the Write-In Progress (WIP) bit to

check if the operation has been completed. The WIP bit will indicate a 1 when the erase cycle is in progress

and a 0 when the erase cycle has been completed. Erase suspend is not allowed during PPB Erase.

Figure 10.66 PPB Erase Command Sequence

10.8.8

PPB Lock Bit Read (PLBRD A7h)

The PPB Lock Bit Read (PLBRD) command allows the PPB Lock Register contents to be read out of SO. It is

possible to read the PPB lock register continuously by providing multiples of eight clock cycles. The PPB Lock

is recommended to check the Write-In Progress (WIP) bit of the Status Register before issuing a new

command to the device.

Figure 10.67 PPB Lock Register Read Command Sequence

CS#

SCK

Phase

Instruction

CS#

SCK

Phase

Instruction

Repeat Register Read

S25FS256S Datasheet(PDF) 128 Page - SPANSION