S25FS256S datasheet(127/154 Pages) SPANSION

127 / 154 page

November 6, 2013 S25FS-S_00_04

S25FS-S Family

127

Da ta

Shee t

(Prelim i nar y )

10.8.5

PPB Read (PPBRD FCh or 4PPBRD E2h)

The instruction E2h is shifted into SI by the rising edges of the SCK signal, followed by the 24- or 32-bit

address, depending on the address length configuration CR2V[7], selecting location zero within the desired

sector (note, the high order address bits not used by a particular density device must be zero). Then the 8-bit

PPB access register contents are shifted out on SO.

It is possible to read the same PPB access register continuously by providing multiples of eight clock cycles.

The address of the PPB register does not increment so this is not a means to read the entire PPB array. Each

location must be read with a separate PPB Read command. The maximum operating clock frequency for the

PPB Read command is 133 MHz.

Figure 10.64 PPBRD Command Sequence

Notes:

1. A = MSB of address = 23 for Address length (CR2V[7] = 0, or 31 for CR2V[7]=1 with command FCh.

2. A = MSB of address = 31 with command E2h.

10.8.6

PPB Program (PPBP FDh or 4PPBP E3h)

Before the PPB Program (PPBP) command can be accepted by the device, a Write Enable (WREN)

command must be issued. After the Write Enable (WREN) command has been decoded, the device will set

the Write Enable Latch (WEL) in the Status Register to enable any write operations.

The PPBP command is entered by driving CS# to the logic low state, followed by the instruction, followed by

the 24- or 32-bit address, depending on the address length configuration CR2V[7], selecting location zero

within the desired sector (note, the high order address bits not used by a particular density device must be

zero).

The PPBP command affects the P_ERR and WIP bits of the Status and Configuration Registers in the same

manner as any other programming operation.

CS# must be driven to the logic high state after the last bit of address has been latched in. If not, the PPBP

command is not executed. As soon as CS# is driven to the logic high state, the self-timed PPBP operation is

initiated. While the PPBP operation is in progress, the Status Register may be read to check the value of the

Write-In Progress (WIP) bit. The WIP bit is a 1 during the self-timed PPBP operation, and is a 0 when it is

completed. When the PPBP operation is completed, the Write Enable Latch (WEL) is set to a 0.

Figure 10.65 PPBP Command Sequence

Notes:

1. A = MSB of address = 23 for Address length (CR2V[7] = 0, or 31 for CR2V[7]=1 with command FDh.

2. A = MSB of address = 31 with command E3h.

CS#

SCK

Phase

Instruction

Address

Repeat Register

CS#

SCK

Phase

Instruction

Address

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