LPC1547JBD48 datasheet(36/99 Pages) NXP

36 / 99 page

LPC15XX

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 19 February 2014

36 of 99

NXP Semiconductors

LPC15xx

32-bit ARM Cortex-M3 microcontroller

– 8 inputs and 10 outputs

– DMA support

• Counter/timer features:

– Configurable as two 16-bit counters or one 32-bit counter.

– Counters clocked by system clock or selected input.

– Configurable as up counters or up-down counters.

– Configurable number of match and capture registers. Up to 16 match and capture

registers total.

– Upon match create the following events: stop, halt, limit counter or change counter

direction; toggle outputs; create an interrupt; change the state.

– Counter value can be loaded into capture register triggered by match or

input/output toggle.

• PWM features:

– Counters can be used in conjunction with match registers to toggle outputs and

create time-proportioned PWM signals.

– Up to eight single-edge or dual-edge controlled PWM outputs with up to eight

independent duty cycles when configured as 32-bit timers.

• Event creation features:

– The following conditions define an event: a counter match condition, an input (or

output) condition such as an rising or falling edge or level, a combination of match

and/or input/output condition.

– Events can only have an effect while the counter is running.

– Selected events can limit, halt, start, or stop a counter or change its direction.

– Events trigger state changes, output toggles, interrupts, and DMA transactions.

– Match register 0 can be used as an automatic limit.

– In bi-directional mode, events can be enabled based on the count direction.

– Match events can be held until another qualifying event occurs.

• State control features:

– A state is defined by the set of events that are allowed to happen in the state.

– A state changes into another state as result of an event.

– Each event can be assigned to one or more states.

– State variable allows sequencing across multiple counter cycles.

• Dither engine.

• Integrated with an input pre-processing unit (SCTIPU) to combine or delay input

events.

Inputs and outputs on the SCTimer0/PWM and SCTimer1/PWM are configured as follows:

• 8 inputs

– 7 inputs. Each input except input 7 can select one of 23 sources from an input

multiplexer.

– One input connected directly to the SCT PLL for a high-speed dedicated clock

input.

LPC1547JBD48 Datasheet(PDF) 36 Page - NXP Semiconductors

LPC1547JBD48 Datasheet(HTML) 36 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99

Datasheet Download

Link URL