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82374EB Datasheet(PDF) 79 Page - Intel Corporation

Part # 82374EB
Description  SYSTEM COMPONENT (ESC)
PDF  208 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

82374EB Datasheet(HTML) 79 Page - Intel Corporation

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82374EB82374SB
335 CAPSCOUNTER ACCESS PORTS
Register Location
040hTimer 1 Counter 0
041hTimer 1 Counter 1
042hTimer 1 Counter 2
048hTimer 2 Counter 0
04AhTimer 2 Counter 2
Default Value
xxh
Attribute
ReadWrite
Size
8 Bits per counter
Each of these IO ports is used for writing count values to the count registers reading the current count value
from the counter by either an IO read after a counter-latch command or after a read-back command and
reading the Status byte following a read-back command
Bit
Description
70
Counter Access
Each counter IO port address is used to program the 16 bit count register The
order of programming either LSB only MSB only or LSB then MSB is defined with the Counter
Control register at IO port address 043h The counter IO port is also used to read the current count
from the count register and return the status of the counter programming following a read-back
command
34 Interrupt Controller Registers
The ESC contains an EISA compatible interrupt controller that incorporates the functionality of two 82C59
interrupt controllers The interrupt registers control the operation of the interrupt controller and can be ac-
cessed from the EISA Bus via IO space This section describes the Interrupt registers The operation of the
Interrupt Controller is described in Chapter 90
341 ICW1INITIALIZATION COMMAND WORD 1
Register Location
020hINT CNTRL-1
0A0hINT CNTRL-2
Default Value
xxh
Attribute
Write Only
Size
8 Bits per controller
A write to Initialization Command Word One starts the interrupt controller initialization sequence Addresses
020h and 0A0h are referred to as the base addresses of CNTRL-1 and CNTRL-2 respectively
An IO write to the CNTRL-1 or CNTRL-2 base address with bit 4 equal to 1 is interpreted as ICW1 For ESC-
based EISA systems three IO writes to ‘‘base address a 1’’ must follow the ICW1 The first write to ‘‘base
address a 1’’ performs ICW2 the second write performs ICW3 and the third write performs ICW4
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