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82374EB Datasheet(PDF) 37 Page - Intel Corporation

Part # 82374EB
Description  SYSTEM COMPONENT (ESC)
PDF  208 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

82374EB Datasheet(HTML) 37 Page - Intel Corporation

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82374EB82374SB
Pin Name
Description
4
General Purpose Chip Selects
This bit is used to select the functionality of the GPCS 20
ECS 20 pins If the bit is set to 0 the GPCS 20
functionality is selected If the bit is set to 1
the ESC 20 functionality is selected
3
System Error
This bit is used to disable (0) or enable (1) the generation of NMI based on
SERR
signal pulsing active When this bit e1 (and NMIs are enabled via the NMIERTC
Register) and SERR
is asserted the NMI signal is asserted When this bit e 0 the NMI signal
is negated and SERR
is disabled from generating an NMI Note that other NMI sources are
enableddisabled via the NMISC Register
20
PIRQx MuxMapping Control
These bits select muxingmapping of PIRQ 30
with
MREQ 74 and group of X-Bus signals (DLIGHT
RTCWR
RTCRD ) Different bit
combinations select the number of EISA slots or group of X-Bus signals which can be
supported with the certain number of PIRQx
signals by determining the functionality of pins
AEN 41 EAEN 41 MACK 30
EMACK 30
MREQ 74
PIRQ 30
DLIGHT
PIRQ0
FDCCS
PIRQ1
RTCWR
PIRQ2
RTCRD
PIRQ3
as shown in Table 1
Table 1 Mode Select Register
20
Bits
Signal Function
AEN 41
MACK 30
MREQ 74
DLIGHT
FDDCS
RTCWR
RTCRD
EAEN 41
EMACK 30
PIRQ 03
PIRQ0
PIRQ1
PIRQ2
PIRQ3
000
EAEN 41
EMACK 30
MREQ 74
PIRQ0
PIRQ1
PIRQ2
PIRQ3
001
EAEN 41
EMACK 30
MREQ 74
PIRQ0
PIRQ1
RTCWR
RTCRD
010
EAEN 41
EMACK 30
MREQ 74
PIRQ0
FDDCS
RTCWR
RTCRD
011
EAEN 41
EMACK 30
MREQ 74
DLIGHT
FDDCS
RTCWR
RTCRD
100
AEN 41
MACK 30
PIRQ 03
DLIGHT
FDDCS
RTCWR
RTCRD
101
EAEN 41
EMACK 30
PIRQ0
DLIGHT
FDDCS
RTCWR
RTCRD
PIRQ1
MREQ5
MREQ4
110
EAEN 41
EMACK 30
PIRQ0
DLIGHT
FDDCS
RTCWR
RTCRD
MREQ6
MREQ5
MREQ4
111
EAEN 41
EMACK 30
MREQ 74
DLIGHT
FDDCS
RTCWR
RTCRD
37



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