82374EB datasheet(55/208 Pages) INTEL

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82374EB82374SB

323 DCEMDMA CHANNEL EXTENDED MODE REGISTER

040BhChannels 0-3

04D6hChannels 4-7

Default Value

000000xxb

Attribute

Write Only

Size

8 Bits

Each channel has an Extended Mode Register The register is used to program the DMA device data size

timing mode EOP inputoutput selection and Stop register selection When writing to the register bits 10

determine which channel’s Extended Mode Register will be written and are not stored Only bits 72 are

stored in the Extended Mode Register Four timing modes are available ISA-compatible A B and Burst

The default bit values for each DMA group are selected upon reset A Master Clear or any other programming

sequence will not set the default register settings The default programmed values for DMA1 Channels 0-3 are

8-bit IO Count by Bytes Compatible timing and EOP output The default values for DMA2 Channels 4-7 are

16-bit IO Count by Words with shifted address Compatible timing and EOP output These default settings

provide a rigorous ISA-compatible DMA implementation

NOTE

DMA1DMA2 refer to the original PC-AT implementation which used two discrete 8237 DMA control-

lers In this context DMA1 refers to DMA Channels 0-3 and DMA2 refers to DMA Channels 4-7 The

PC-AT used Channel 4 (Channel 0 of DMA2) as a cascade channel for DMA1 Consequently Chan-

nel 4 is not used in compatible DMA controllers although the compatible DMA registers are kept to

maintain compatibility with the original PC-AT Because Channel 4 is not used the DMA controller

does not support extended registers for Channel 4

Bit

Description

Stop Register

Bit 7 of this register selects whether or not the Stop registers associated with this

channel are to be used Normally the Stop Registers will not be used This function was added to help

support data communication or other devices that work from a ring buffer in memory Upon reset the

bit 7 is set to 0-Stop register disabled The detailed Stop register functional description discusses the

use of the Stop registers

EOP InputOutput

Bit 6 of the Extended Mode register selects whether the EOP signal is to be used

as an output during DMA on this channel or an input EOP will generally be used as an output as was

available on the PCAT The input function was added to support Data Communication and other

devices that would like to trigger an autoinitialize when a collision or some other event occurs The

direction of EOP is switched when DACK is changed (when a different channel wins the arbitration and

is granted the bus) There may be some overlap of the ESC driving the EOP signal along with the DMA

slave However during this overlap both devices will be driving the signal to a low level (negated) For

example assume Channel 2 is about to go inactive (DACK negated) and channel 1 is about to go

active If Channel 2 is programmed for ‘‘EOP OUT’’ and Channel 1 is programmed for ‘‘EOP IN’’ when

Channel 2’s DACK is negated and Channel 1’s DACK is asserted the ESC may be driving EOP to a

low value on behalf of Channel 2 at the same time the device connected to Channel 1 is driving EOP in

to the ESC also at an inactive level This overlap will only last until the ESC EOP output buffer is

tristated and will not effect the DMA operation Upon reset the value of bit 6 is 0 (EOP output

selected)

82374EB Datasheet(PDF) 55 Page - Intel Corporation

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