82374EB datasheet(19/208 Pages) INTEL

19 / 208 page

82374EB82374SB

Pin Name

Type

Description

LA 3127

EISA ADDRESS BUSCONFIGURATION RAM PAGE ADDRESS

These are

multiplexed signals These signals behave as the EISA address bus under all

CPG 40

conditions except during access cycle to the Configuration RAM

EISA Address Bus LA 3127

are directly connected to the EISA address bus

The ESC uses the address bus in conjunction with the BE 30

signals as inputs to

decode accesses to its internal resources except in DMA and Refresh modes

During DMA and Refresh modes these are outputs and the ESC uses these signals

in conjunction with BE 30

to drive Memory address

Configuration Ram Page Address CPG 40 are connected to Configuration SRAM

address lines During IO access to 0800h-08FFh the ESC drives these signals with

the configuration page address (the value contained in register 0C00h) The

Configuration RAM Page Address function can be disabled by setting Mode Select

LA 2624

EISA ADDRESS BUS

These signals are directly connected to the EISA address

bus The ESC uses the address bus in conjunction with the BE 30

signals as

and

inputs to decode accesses to its internal resources except in DMA and Refresh

LA 232

modes During DMA and Refresh modes these are outputs and the ESC uses

these signals in conjunction with BE 30

to drive Memory address

BE 30

BYTE ENABLES

BE 30

signals are directly connected to the EISA address bus

These signals indicate which byte on the 32-bit EISA data bus are involved in the

current cycle BE 30

are inputs during EISA master cycles which do not require

assemblydisassembly operation For EISA master assemblydisassembly cycles

ISA master cycles DMA and Refresh cycles BE 30

are outputs

BE0

Corresponds to byte lane 0-SD 70

BE1

Corresponds to byte lane 0-SD 158

BE2

Corresponds to byte lane 0-SD 2316

BE3

Corresponds to byte lane 0-SD 3124

MIO

MEMORY OR IO CYCLE

MIO

signal is used to differentiate between memory

cycles and IO cycles on the EISA bus A High value on this signal indicates a

memory cycle and a Low value indicates an IO cycle MIO

is an input to the

ESC during EISA master cycles and MIO

is an output during ISA DMA and ESC

initiated Refresh cycles MIO

is floated during ISA master initiated Refresh

cycles

WRITE OR READ CYCLE

signal is used to differentiate between write and

read cycles on the EISA bus A High value on this signal indicates a Write cycle and

a Low value indicates a Read cycle WR

is an input to the ESC during EISA

master cycles and WR

is an output during ISA DMA and Refresh cycles

82374EB Datasheet(PDF) 19 Page - Intel Corporation

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