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82374EB Datasheet(PDF) 30 Page - Intel Corporation |
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82374EB Datasheet(HTML) 30 Page - Intel Corporation |
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30 / 208 page  82374EB82374SB 211 Integrated Logic Signals 2111 EISA ADDRESS BUFFER CONTROL Pin Name Type Description SALE out SA LATCH ENABLE SALE is directly connected to F543s which buffer the LA addresses from the SA addresses The rising edge of SALE latches the LA address bit LA 192 to the SA address bit SA 192 LASAOE out LA TO SA ADDRESS OUTPUT ENABLE LASAOE is directly connected to the SA output buffer enables of the F543s The ESC asserts LASAOE during EISA master cycles When LASAOE is asserted the LA to SA output buffers of the F543s are enabled SALAOE out SA TO LA ADDRESS OUTPUT ENABLE SALAOE is connected to the LA output buffer enables of the F543s This signal functionally is the exact opposite of LASAOE signals The ESC asserts SALAOE during ISA master cycles When LASAOE is asserted the SA to LA output buffers of the F543s are enabled 2112 COPROCESSOR INTERFACE Pin Name Type Description FERR in NUMERIC CO-PROCESSOR ERROR FERR signal is tied to the Co-processor error signal of the CPU If FERR is asserted (Co-processor error detected by the CPU) an internal IRQ13 is be generated and the INTR from the ESC will be asserted IGNNE out IGNORE NUMERIC ERROR IGNNE is tied to the ignore numeric error pin of the CPU IGNNE is asserted and internal IRQ13 is negated from the falling edge of IOWC during an IO write to location 00F0h IGNNE will remain asserted until FERR is negated During reset this signal is driven low 2113 BIOS INTERFACE Pin Name Type Description LBIOSCS out LATCHED BIOS CHIP-SELECT LBIOSCS indicates the that the current address is for the system BIOS The ESC generates this signal by decoding the EISA LA addresses The ESC uses a transparent latch to latch the decoded signal The LBIOSCS is latched on the falling edge of BALE and qualified with REFRESH 30 |
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