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82374EB Datasheet(PDF) 52 Page - Intel Corporation |
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82374EB Datasheet(HTML) 52 Page - Intel Corporation |
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52 / 208 page  82374EB82374SB 3124 CTLTMRCLOCK SCALE STPCLK LOW TIMER Address Offset ACh Default Value 00h Attribute ReadWrite Size 8 Bits For the 82374SB the value in this register defines the duration of the STPCLK asserted period when bit 2 in the SMICNTL Register is set to 1 The value in this register is loaded into the STPCLK Timer when STPCLK is asserted However the timer does not start until the Stop Grant Bus Cycle is received The STPCLK timer counts using a 32 ms clock Bit Description 70 Clock Scaling STPCLK Low Timer Value Bits 70 define the duration of the STPCLK asserted period during clock throttling 3125 CTLTMRHCLOCK SCALE STPCLK HIGH TIMER Address Offset AEh Default Value 00h Attribute ReadWrite Size 8 Bits For the 82374SB the value in this register defines the duration of the STPCLK negated period when bit 2 in the SMICNTL Register is set to 1 The value in this register is loaded into the STPCLK Timer when STPCLK is negated The STPCLK timer counts using a 32 ms clock Bit Description 70 Clock Scaling STPCLK High Timer Value Bits 70 define the duration of the STPCLK negated period during clock throttling 32 DMA Register Description The ESC contains DMA circuitry that incorporates the functionality of two 82C37 DMA controllers (DMA1 and DMA2) The DMA registers control the operation of the DMA controllers and are all accessible from the EISA Bus This section describes the DMA registers Unless otherwise stated a reset sets each register to its default value The operation of the DMA is further described in Chapter 60 DMA Controller 321 DCOMCOMMAND REGISTER Register Location 08hChannels 0-3 0D0hChannels 4-7 Default Value 00h Attribute Write Only Size 8 Bits This 8-bit register controls the configuration of the DMA It is programmed by the microprocessor in the Program Condition and is cleared by reset or a Master Clear instruction Note that disabling Channels 4-7 will also disable Channels 0-3 since Channels 0-3 are cascaded onto Channel 4 The DREQ and DACK channel assertion sensitivity is assigned by channel group not per individual Channel For priority resolution the DMA 52 |
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