82374EB datasheet(18/208 Pages) INTEL

18 / 208 page

82374EB82374SB

The following notations are used to describe the signal type

Input is a standard input-only signal

out

Totem Pole Output is a standard active driver

Open Drain InputOutput

Tri-State is a bi-directional tri-state inputoutput pin

sts

Sustained Tri-State is an active low tri-state signal owned and driven by one and only one agent at a

time The agent that drives a sts pin low must drive it high for at least one clock before letting it float

A new agent can not start driving a sts signal any sooner than one clock after the previous owner tri-

states it A pull-up sustains the inactive state until another agent drives it and is provided by the central

resource

NOTE

During a hard reset INTR NMI IGNNE

SMI

(on 82374SB) ALTRST

STPCLK

(on 82374SB)

and ALTA20 are driven low to prevent problems associated with 5V33V power sequencing Any

outputs of the ESC that are directed to a 33V CPU must be driven through a 5V to 33V translator

21 PCI Local Bus Interface Signals

Pin Name

Type

Description

PCICLK

PCI CLOCK

PCICLK provides timing for all transactions on the PCI bus The ESC uses

the PCI Clock (PCICLK) to generate EISA Bus Clock (BCLK) The PCICLK is divided by

3 or 4 to generate the BCLK The EISA Bridge supports PCI Clock frequencies of

25 MHz through 33 MHz

PERR

PARITY ERROR

PERR

indicates a data parity error PERR

may be pulsed active

by any agent that detects an error condition Upon sampling PERR

active the ESC

generates an NMI interrupt to the CPU

SERR

SYSTEM ERROR

SERR

may be pulsed active by any agent that detects an error

condition Upon sampling SERR

active the ESC generates an NMI interrupt to the

CPU

RESET

SYSTEM RESET

RESET

forces the entire ESC chip into a known state All internal

ESC state machines are reset and all registers are set to their default values RESET

may be asynchronous to PCICLK when asserted or negated Although asynchronous

negation must be a clean bounce-free edge The ESC uses RESET

to generate

RSTDRV signal

22 EISA Bus Interface Signals

Pin Name

Type

Description

BCLKOUT

out

EISA BUS CLOCK OUTPUT

BCLKOUT is typically buffered to create EISA Bus Clock

(BCLK) The BCLK is the system clock used to synchronize events on the EISAISA

bus The BCLKOUT is generated by dividing the PCICLK The ESC uses a divide by 3

or divide by 4 to generate the BCLKOUT

BCLK

EISA BUS CLOCK

The ESC uses BCLK to synchronize events on the EISA bus The

ESC generates or samples all the EISAISA bus signals on either the rising or the

falling edge of BCLK

82374EB Datasheet(PDF) 18 Page - Intel Corporation

82374EB Datasheet(HTML) 18 Page - Intel Corporation

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