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AN4650 Datasheet(PDF) 94 Page - STMicroelectronics

Part # AN4650
Description  This document is intended to provide usage information
PDF  102 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

AN4650 Datasheet(HTML) 94 Page - STMicroelectronics

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First-in first-out (FIFO) buffer
AN4650
94/102
DocID027415 Rev 1
8.8
Step counter and time stamp data in FIFO
It is possible to store timestamp and step counter data in the FIFO. These data are stored as
a 4th FIFO data set in the 6-byte data format shown in Table 75:
3 bytes for the time stamp;
1 byte is not used;
2 bytes for the number of steps.
To enable this feature, the bit TIMER_PEDO_FIFO_EN must be set to 1 in the FIFO_CTRL2
register.
When this feature is enabled, the 6 bytes containing the timestamp and Step Counter data
are associated to the 4th FIFO data set: the DEC_DS4_FIFO[2:0] field of FIFO_CTRL4
register has to be used to define the decimator factor.
When this feature is enabled and the DATA_VALID_SEL_FIFO bit of the
MASTER_CONFIG register is set to 0, data can be stored in the FIFO in two ways,
depending on the configuration of the TIMER_PEDO_FIFO_DRDY bit in FIFO_CTRL2:
When the TIMER_PEDO_FIFO_DRDY bit is set to 0, data are written to the FIFO at
the ODR_FIFO rate set in the FIFO_CTRL5 register.
When the TIMER_PEDO_FIFO_DRDY bit is set to 1, data are stored in the FIFO every
time a new step is detected.
Follow these steps to store time stamp and pedometer data in the FIFO using either the
internal trigger (accelerometer/gyroscope data ready) or the ‘step detected’ method:
1.
Turn on the accelerometer;
2.
Enable the time stamp and pedometer (see Section 5.1 and Section 5.4);
3.
Choose the decimation factor for the 4th FIFO data set through the
DEC_DS4_FIFO[2:0] bits of the FIFO_CTRL4 register;
4.
Set to 1 the TIMER_PEDO_FIFO_EN bit in the FIFO_CTRL2 register;
5.
Configure the bit TIMER_PEDO_FIFO_DRDY in the FIFO_CTRL2 register, in order to
choose when storing data in the FIFO (internal trigger or every step detected);
6.
If an internal trigger is used, choose the FIFO ODR through the ODR_FIFO_[3:0] bits of
the FIFO_CTRL5 register. If ‘step detected’ trigger is used, no need to set the
ODR_FIFO_[3:0] bits;
7.
Configure the FIFO operating mode through the FIFO_MODE_[2:0] field of the
FIFO_CTRL5 register.
Table 75. Timestamp and pedometer data in FIFO
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
TIMESTAMP
[15:8]
TIMESTAMP
[23:16]
-
TIMESTAMP
[7:0]
STEPS
[7:0]
STEPS
[15:8]



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