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AN4650

Interrupt generation

102

Tap interrupt signals can also be checked by reading the TAP_SRC (1Ch) register,

described in Table 32.



TAP_IA is set high when a single-tap or double-tap event has been detected.



SINGLE_TAP is set high when a single tap has been detected.



DOUBLE_TAP is set high when a double tap has been detected.



TAP_SIGN indicates the acceleration sign when the tap event is detected. It is set low

in case of positive sign and it is set high in case of negative sign.



X_TAP (Y_TAP, Z_TAP) is set high when the tap event has been detected on the X (Y,

Z) axis

Single and double-tap recognition works independently. Setting the SINGLE_DOUBLE_TAP

bit of WAKE_UP_THS to 0, only the single-tap recognition is enabled: double-tap

recognition is disabled and cannot be detected. When the SINGLE_DOUBLE_TAP is set to

1, both single and double-tap recognition are enabled.

If the latch mode is enabled and the interrupt signal is driven to the interrupt pins, the value

assigned to SINGLE_DOUBLE_TAP also affects the behavior of the interrupt signal: when it

is set to 0, the latch mode is applied to the single-tap interrupt signal; when it is set to 1, the

latch mode is applied to the double-tap interrupt signal only. The latched interrupt signal is

kept high until the TAP_SRC register is read. If the latch mode is enabled but the interrupt

signal is not driven to the interrupt pins, the latch feature does not take effect.

4.5.4

Single-tap example

Hereafter an example code which implements the SW routine for single-tap detection.

In this example the TAP_THS fied of the TAP_THS_6D register is set to 01001b, therefore

the tap threshold is 562.5 mg (= 9 * FS_XL / 25).

The SHOCK field of the INT_DUR2 register is set to 10b: an interrupt is generated when the

slope data exceeds the programmed threshold, and returns below it within 38.5 ms (= 2 * 8 /

ODR_XL) corresponding to the Shock time window.

The QUIET field of the INT_DUR2 register is set to 01b: since the latch mode is disabled,

the interrupt is kept high for the duration of the Quiet window, therefore 9.6 ms (= 1 * 8 /

ODR_XL.)

Table 32. TAP_SRC register

TAP_IA

SINGLE

_TAP

DOUBLE

_TAP

TAP_SIGN

X_TAP

Y_TAP

Z_TAP

Write 60h into CTRL1_XL

// Turn on the accelerometer

// ODR_XL = 416 Hz, FS_XL = 2g

Write 0Eh into TAP_CFG

// Enable tap detection on X, Y, Z axis

Write 09h into TAP_THS_6D

// Set tap threshold

Write 06h into INT_DUR2

// Set Quiet and Shock time windows

Write 00h into WAKE_UP_THS

// Only single tap enabled (SINGLE_DOUBLE_TAP = 0)

Write 40h into MD1_CFG

// Single tap interrupt driven to INT1 pin

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