DP83867CS datasheet(28/114 Pages) TI1

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DP83867CS, DP83867IS, DP83867E

SNLS504 – OCTOBER 2015

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9.4.2.9 Example of Write Operation Using Indirect Register Access

Write register 0x0170 to value 0x0C50.

1. Write register 0x0D to value 0x001F.

2. Write register 0x0E to value 0x0170

3. Write register 0x0D to value 0x401F.

4. Write register 0x0E to value 0x0C50.

This write will disable the output clock on the CLK_OUT pin.

9.4.3 Auto-Negotiation

All 1000BASE-T PHYs are required to support Auto-Negotiation. The Auto-Negotiation function in 1000BASE-T

has three primary purposes:

•

Auto-Negotiation of Speed & Duplex Selection

•

Auto-Negotiation of Master/Slave Resolution

•

Auto-Negotiation of Pause/Asymetrical Pause Resolution

9.4.3.1 Speed/Duplex Selection - Priority Resolution

The Auto-Negotiation function provides a mechanism for exchanging configuration information between the two

ends of a link segment. This mechanism is implemented by exchanging Fast Link Pulses (FLP). FLPs are burst

pulses that provide the signalling used to communicate the abilities between two devices at each end of a link

segment. For further details regarding Auto-Negotiation, refer to Clause 28 of the IEEE 802.3 specification. The

DP83867 supports 1000BASE-T, 100BASE-TX, and 1000BASE-T modes of operation. The process of Auto-

Negotiation ensures that the highest performance protocol is selected (i.e., priority resolution) based on the

advertised abilities of the Link Partner and the local device.

9.4.3.2 Master/Slave Resolution

If 1000BASE-T mode is selected during the priority resolution, the second goal of Auto-Negotiation is to resolve

Master/ Slave configuration. The Master mode priority is given to the device that supports multiport nodes, such

as switches and repeaters. Single node devices such as DTE or NIC card takes lower Master mode priority.

9.4.3.3 Pause and Asymmetrical Pause Resolution

When Full-Duplex operation is selected during priority resolution, the Auto-Negotiation also determines the Flow

Control capabilities of the two link partners. Flow control was originally introduced to force a busy station’s Link

Partner to stop transmitting data in Full-Duplex operation. Unlike Half-Duplex mode of operation where a link

partner could be forced to back off by simply generating collisions, the Full-Duplex operation needed a

mechanism to slow down transmission from a link partner in the event that the receiving station’s buffers are

becoming full. A new MAC control layer was added to handle the generation and reception of Pause Frames.

Each MAC Controller has to advertise whether it is capable of processing Pause Frames. In addition, the MAC

Controller advertises if Pause frames can be handled in both directions, i.e. receive and transmit. If the MAC

Controller only generates Pause frames but does not respond to Pause frames generated by a link partner, it is

called Asymmetrical Pause. The advertisement of Pause and Asymmetrical Pause capabilities is enabled by

writing ‘1’ to bits 10 and 11 of ANAR (register address 0x0004). The link partner’s Pause capabilities is stored in

ANLPAR (register address 0x0005) bits 10 and 11. The MAC Controller has to read from ANLPAR to determine

which Pause mode to operate. The PHY layer is not involved in Pause resolution other than simply advertising

and reporting of Pause capabilities.

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