DP83867CS datasheet(5/114 Pages) TI1

5 / 114 page

DP83867CS, DP83867IS, DP83867E

www.ti.com

SNLS504 – OCTOBER 2015

Table 2. Pin Functions (continued)

TYPE(1)

DESCRIPTION

NAME

NUMBER

RECEIVE DATA Bit 3: This signal carries data from the PHY to the MAC in

RX_D3

O, PD

RGMII mode. It is synchronous to the receive clock RX_CLK.

TRANSMIT CONTROL: In RGMII mode, it combines the transmit enable and

TX_CTRL

I, PD

the transmit error signals of GMII mode using both clock edges.

RECEIVE CONTROL: In RGMII mode, the receive data available and receive

RX_CTRL

S, O, PD

error are combined (RXDV_ER) using both rising and falling edges of the

receive clock (RX_CLK).

GENERAL PURPOSE I/O

General Purpose I/O: This signal provides a multi-function configurable I/O.

GPIO_0

S, O, PD

Please refer to the GPIO_MUX_CTRL register for details.

General Purpose I/O: This signal provides a multi-function configurable I/O.

GPIO_1

S, O, PD

Please refer to the GPIO_MUX_CTRL register for details.

MANAGEMENT INTERFACE

MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO serial

management input/output data. This clock may be asynchronous to the MAC

MDC

I, PD

transmit and receive clocks. The maximum clock rate is 25MHz and no

minimum.

MANAGEMENT DATA I/O: Bi-directional management instruction/data signal

that may be sourced by the management station or the PHY. This pin requires

MDIO

I/O

pullup resistor. The IEEE specified resistor value is 1.5k

Ω, but a 2.2kΩ is

acceptable.

INTERRUPT / POWER DOWN:

The default function of this pin is POWER DOWN.

POWER DOWN: This is an Active Low Input. Asserting this signal low enables

the Power Down mode of operation. In this mode, the device will power down

and consume minimum power. Register access will be available through the

INT / PWDN

I/O, PU

Management Interface to configure and power up the device.

INTERRUPT: This pin may be programmed as an interrupt output instead of a

Powerdown input. In this mode, Interrupts will be asserted low using this pin

making it an active low output. Register access is required for the pin to be

used as an interrupt mechanism. When operating this pin as an interrupt, an

external 2.2k

Ω connected to the VDDIO supply is recommended.

RESET

RESET: The active low RESET initializes or re-initializes the DP83867. All

RESET_N

I, PU

internal registers will re-initialize to their default state upon assertion of RESET.

The RESET input must be held low for a minimum of 1µs.

CLOCK INTERFACE

CRYSTAL/OSCILLATOR INPUT: 25 MHz oscillator or crystal input (50 ppm)

CRYSTAL OUTPUT: Second terminal for 25 MHz crystal. Must be left floating if

a clock oscillator is used.

CLK_OUT

CLOCK OUTPUT: Output clock

JTAG INTERFACE

JTAG TEST CLOCK: IEEE 1149.1 Test Clock input, primary clock source for all

JTAG_CLK

I, PU

test logic input and output controlled by the testing entity.

JTAG TEST DATA OUTPUT: IEEE 1149.1 Test Data Output pin, the most

JTAG_TDO

recent test results are scanned out of the device via TDO.

JTAG TEST MODE SELECT: IEEE 1149.1 Test Mode Select pin, the TMS pin

sequences the Tap Controller (16-state FSM) to select the desired test

JTAG_TMS

I, PU

instruction. It is recommended to apply 3 clock cycles with JTAG_TMS high to

reset the JTAG.

JTAG TEST DATA INPUT: IEEE 1149.1 Test Data Input pin, test data is

JTAG_TDI

I, PU

scanned into the device via TDI.

LED INTERFACE

LED_2: By default, this pin indicates receive or transmit activity. Additional

LED_2

S, I/O, PD

functionality is configurable via LEDCR1[11:8] register bits.

Submit Documentation Feedback

DP83867CS Datasheet(PDF) 5 Page - Texas Instruments

DP83867CS Datasheet(HTML) 5 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL