DP83867CS datasheet(41/114 Pages) TI1

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2.49

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VDDIO

RX_D0

6.04

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2.49

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VDDIO

RX_D2

DP83867CS, DP83867IS, DP83867E

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SNLS504 – OCTOBER 2015

9.5.4 PHY Address Configuration

The DP83867 can be set to respond to any of 16 possible PHY addresses via strap pins. The information is

latched into the device at a device power up or hardware reset. Each DP83867 or port sharing an MDIO bus in a

system must have a unique physical address. The DP83867 supports PHY address strapping values 0 (<0000>)

through 15 (<1111>).

For further detail relating to the latch-in timing requirements of the PHY Address pins, as well as the other

hardware configuration pins, refer to Reset Operation.

Based on the default strap configuration of PHY_ADD[3:0], the DP83867 PHY address will initialize to 0x00

without any external strap configuration.

Refer to Figure 20 for an example of a PHY address connection to external components. In this example, the

pins are configured as follows: RX_D2 = Strap Mode 3 and RX_D0 = Strap Mode 2. Therefore, the PHY address

strapping results in address 1001 (09h).

Figure 20. PHY Address Strapping Example

When operating in SGMII mode, dummy straps must be added to provide a balanced load for the SGMII

differential pairs. Therefore, for SGMII applications with the straps shown in Figure 20, the corresponding

connections for RX_D1 and RX_D3 are shown in Figure 21.

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DP83867CS Datasheet(PDF) 41 Page - Texas Instruments