DP83867CS datasheet(76/114 Pages) TI1

76 / 114 page

DP83867CS, DP83867IS, DP83867E

SNLS504 – OCTOBER 2015

www.ti.com

9.6.26 Control Register (CTRL)

Table 37. Control Register (CTRL), Address 0x001F

BIT

BIT NAME

DEFAULT

DESCRIPTION

SW_RESET

0, RW, SC

Software Reset:

1 = Perform a full reset, including registers.

0 = Normal operation.

SW_RESTART

0, RW, SC

Software Restart:

1 = Perform a full reset, not including registers. .

0 = Normal operation.

13:0

RESERVED

0, RO

RESERVED: Writes ignored, read as 0.

9.6.27 Testmode Channel Control (TMCH_CTRL)

Table 38. Testmode Channel Control (TMCH_CTRL), Address 0x0025

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:8

RESERVED

0x04

RESERVED

7:5

TM_CH_SEL

0x0

Test mode Channel Select.

If bit 7 is set then Test mode is driven on all 4 channels. If bit 7 is

cleared then test modes are driven according to bits 6:5 as follows:

00: Channel A

01: Channel B

10: Channel C

11: Channel D

4:0

RESERVED

0x00

RESERVED

9.6.28 Configuration Register 4 (CFG4)

Table 39. Configuration Register 4 (CFG4), Address 0x0031

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:8

RESERVED

0, RO

RESERVED

0, RO

RESERVED

6:5

SGMII_AUTONEG_TIMER

01, RW

SGMII Auto-Negotiation Timer Duration:

11: 11ms

10: 800us

01: 2us

00: 16ms

4:1

RESERVED

1000, RO

RESERVED: Writes ignored, read as 1000.

PORT_MIRROR_EN

0, RW

Port Mirror Enable:

1 = Enable port mirroring.

0 = Normal operation

9.6.29 RGMII Control Register (RGMIICTL)

This register provides access to the RGMII controls.

Table 40. RGMII Control Register (RGMIICTL), Address 0x0032

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:8

RESERVED

0, RO

RESERVED: Writes ignored, read as 0.

RGMII_EN

1, RW

RGMII Enable:

1 = Enable RGMII interface.

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