DP83867CS datasheet(96/114 Pages) TI1

96 / 114 page

DP83867CS, DP83867IS, DP83867E

SNLS504 – OCTOBER 2015

www.ti.com

9.6.88 TDR General Configuration Register 1 (TDR_GEN_CFG1)

Table 99. TDR General Configuration Register 1 (TDR_GEN_CFG1), Address 0x0180

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:13

RESERVED

0, RO

RESERVED

TDR_CH_CD_BYPASS

0, RW

TDR Bypass for Channel C and D:

1 = Bypass channel C and D in TDR tests.

0 = Normal operation.

TDR_CROSS_MODE_DIS

0, RW

Disable TDR Cross Mode:

1 = Disable cross mode option. Do not check cross channels. Only

listen to the channel being used for transmit.

0 = Normal operation.

TDR_NLP_CHECK

1, RW

TDR NLP Check:

1 = Check for NLPs during silence.

0 = Normal operation.

9:7

TDR_AVG_NUM

110, RW

Number Of TDR Cycles to Average:

111: RESERVED: Writes ignored, read as 0.

110: 64 TDR cycles

101: 32 TDR cycles

100: 16 TDR cycles

011: 8 TDR cycles

010: 4 TDR cycles

001: 2 TDR cycles

000: 1 TDR cycle

6:4

TDR_SEG_NUM

101, RW

Set the number of TDR segments to check.

3:0

TDR_CYCLE_TIME

010, RW

Set the time for each TDR cycle. Value is measured in

microseconds.

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