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DP83867CS Datasheet(PDF) 87 Page - Texas Instruments

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Part # DP83867CS
Description  High Immunity, Small Form Factor 10/100/1000 Ethernet Physical Layer Transceiver
PDF  114 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

DP83867CS Datasheet(HTML) 87 Page - Texas Instruments

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DP83867CS, DP83867IS, DP83867E
www.ti.com
SNLS504 – OCTOBER 2015
9.6.42 Pattern Match Data Register 1 (RXFPMD1)
Table 53. Pattern Match Data Register 1 (RXFPMD1), Address 0x0136
BIT
BIT NAME
DEFAULT
DESCRIPTION
15:0
PMATCH_DATA_15_0
0, RW
Bits 15:0 of Perfect Match Data - used for DA (destination address)
match
9.6.43 Pattern Match Data Register 2 (RXFPMD2)
Table 54. Pattern Match Data Register 2 (RXFPMD2), address 0x0137
BIT
BIT NAME
DEFAULT
DESCRIPTION
15:0
PMATCH_DATA_31_16
0, RW
Bits 31:16 of Perfect Match Data - used for DA (destination address)
match
9.6.44 Pattern Match Data Register 3 (RXFPMD3)
Table 55. Pattern Match Data Register 3 (RXFPMD3), address 0x0138
BIT
BIT NAME
DEFAULT
DESCRIPTION
15:0
PMATCH_DATA_ 47_32
0, RW
Bits 47:32 of Perfect Match Data - used for DA (destination address)
match
9.6.45 SecureOn Pass Register 2 (RXFSOP1)
Table 56. SecureOn Pass Register 1 (RXFSOP1), Address 0x0139
BIT
BIT NAME
DEFAULT
DESCRIPTION
15:0
SCRON_PASSWORD _15_0
0, RW
Bits 15:0 of secure-on password for magic packet)
9.6.46 SecureOn Pass Register 2 (RXFSOP2)
Table 57. SecureOn Pass Register 2 (RXFSOP2), Address 0x013A
BIT
BIT NAME
DEFAULT
DESCRIPTION
15:0
SCRON_PASSWORD _31_16
0, RW
Bits 31:16 of secure-on password for magic packet
9.6.47 SecureOn Pass Register 3 (RXFSOP3)
Table 58. SecureOn Pass Register 3 (RXFSOP3), Address 0x013B
BIT
BIT NAME
DEFAULT
DESCRIPTION
15:0
SCRON_PASSWORD _ 47_32
0, RW
Bits 47:32 of secure-on password for magic packet
9.6.48 Receive Pattern Register 1 (RXFPAT1)
Table 59. Receive Pattern Register 1 (RXFPAT1), Address 0x013C
BIT
BIT NAME
DEFAULT
DESCRIPTION
15:0
PATTERN_BYTES_0_1
0, RW
Bytes 0 (LSbyte) + 1 of the configured pattern. Each byte can be
masked separately via the RXF_PATTERN_BYTE_MASK registers.
9.6.49 Receive Pattern Register 2 (RXFPAT2)
Table 60. Receive Pattern Register 2 (RXFPAT2), Address 0x013D
BIT
BIT NAME
DEFAULT
DESCRIPTION
15:0
PATTERN_BYTES_2_3
0, RW
Bytes 2 + 3 of the configured pattern. Each byte can be masked
separately via the RXF_PATTERN_BYTE_MASK registers.
Copyright © 2015, Texas Instruments Incorporated
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