DP83867CS datasheet(34/114 Pages) TI1

34 / 114 page

DP83867CS, DP83867IS, DP83867E

SNLS504 – OCTOBER 2015

www.ti.com

The Fast Link Down functionality allows the use of each of these options separately or in any combination. Note

that since this mode enables extremely quick reaction time, it is more exposed to temporary bad link quality

scenarios.

9.4.6.5 Fast Link Detect

Several advanced modes are available for fast link establishment. Unlike the Auto-Negotiation and Auto-MDIX

mechanisms defined by the IEEE 802.3 specification, these modes are specific to the DP83867. Care must be

taken when implementing these modes. For best operation, it is recommended that these modes be

implemented with a DP83867 on both ends of the link.

These advanced link and crossover modes depend on the speed selected for the link. Some modes are intended

for use in 1000Base-T operation. Others are intended for use in 100Base-TX operation.

Fast Link Detect functionality can be configured using the Configuration Register 3 (CFG3), address 0x001E.

9.4.6.6 Speed Optimization

Speed optimization, also known as link downshift, enables fallback to 100M operation after multiple consecutive

failed attempts at Gigabit link establishment. Such a case could occur if cabling with only four wires (two twisted

pairs) were connected instead of the standard cabling with eight wires (four twisted pairs).

The number of failed link attempts before falling back to 100M operation is configurable. By default, four failed

link attempts are required before falling back to 100M.

In enhanced mode, fallback to 100M can occur after one failed link attempt if energy is not detected on the C and

D channels. Speed optimization also supports fallback to 10M if link establishment fails in Gigabit and in 100M

mode.

Speed optimization can be enabled via register configuration.

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DP83867CS Datasheet(PDF) 34 Page - Texas Instruments