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DP83867CS Datasheet(PDF) 67 Page - Texas Instruments

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Part # DP83867CS
Description  High Immunity, Small Form Factor 10/100/1000 Ethernet Physical Layer Transceiver
PDF  114 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

DP83867CS Datasheet(HTML) 67 Page - Texas Instruments

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DP83867CS, DP83867IS, DP83867E
www.ti.com
SNLS504 – OCTOBER 2015
9.6.18 Configuration Register 2 (CFG2)
Table 29. Configuration Register 2 (CFG2), Address 0x0014
BIT
BIT NAME
DEFAULT
DESCRIPTION
15:14
RESERVED
0, RO
RESERVED: Writes ignored, read as 0.
13
INTERRUPT_POLARITY
1, RW
Configure Interrupt Polarity:
1 = Interrupt pin is active low.
0 = Interrupt pin is active high.
12
RESERVED
0, RO
RESERVED
11:10
SPEED_OPT_ATTEMPT_CNT
10, RO
Speed Optimization Attempt Count:
Selects the number of 1000BASE-T link establishment attempt
failures prior to performing Speed Optimization.
11 = 8
10 = 4
01 = 2
00 = 1
9
SPEED_OPT_EN
1, RW
Speed Optimization Enable:
1 = Enable Speed Optimization.
0 = Disable Speed Optimization.
8
SPEED_OPT_ENHANCED_EN
1, RW
Speed Optimization Enhanced Mode Enable:
In enhanced mode, speed is optimized if energy is not detected in
channels C and D.
1 = Enable Speed Optimization enhanced mode.
0 = Disable Speed Optimization enhanced mode.
7
SGMII_AUTONEG_EN
1, RW
SGMII Auto-Negotiation Enable:
1 = Enable SGMII Auto-Negotaition.
0 = Disable SGMII Auto-Negotaition.
6
SPEED_OPT_10M_EN
1, RW
Enable Speed Optimization to 10BASE-Te:
1 = Enable speed optimization to 10BASE-Te if link establishment
fails in 1000BASE-T and 100BASE-TX .
0 = Disable speed optimization to 10BASE-Te.
5:0
RESERVED
0, RO
RESERVED
9.6.19 Receiver Error Counter Register (RECR)
Table 30. Receiver Error Counter Register (RECR), Address 0x0015
BIT
BIT NAME
DEFAULT
DESCRIPTION
15:0
RXERCNT[15:0]
0, RO, WSC
RX_ER Counter:
Receive error counter. This register saturates at the maximum value
of 0xFFFF. It is cleared by dummy write to this register.
Copyright © 2015, Texas Instruments Incorporated
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