DP83867CS datasheet(94/114 Pages) TI1

94 / 114 page

DP83867CS, DP83867IS, DP83867E

SNLS504 – OCTOBER 2015

www.ti.com

9.6.86 I/O Configuration (IO_MUX_CFG)

Table 97. I/O Configuration (IO_MUX_CFG), Address 0x0170

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:13

RESERVED

0, RO

RESERVED

12:8

CLK_O_SEL

0 0110, RW

Clock Output Select:

01101 - 11111: RESERVED

01100: Reference clock (synchronous to X_I input clock)

01011: Channel D transmit clock

01010: Channel C transmit clock

01001: Channel B transmit clock

01000: Channel A transmit clock

00111: Channel D receive clock divided by 5

00110: Channel C receive clock divided by 5

00101: Channel B receive clock divided by 5

00100: Channel A receive clock divided by 5

00011: Channel D receive clock

00010: Channel C receive clock

00001: Channel B receive clock

00000: Channel A receive clock

RESERVED

0, RO

RESERVED

CLK_O_DISABLE

Strap, RW

Clock Output Disable:

1 = Disable clock output on CLK_OUT pin.

0 = Enable clock output on CLK_OUT pin.

RESERVED

0, RO

RESERVED

4:0

IO_IMPEDANCE_CTRL

10000, RW

Impedance Control for MAC I/Os:

11100: I/O adjustment for external loopback testing on the MAC

interface.

Other values for this register are not recommended.

Submit Documentation Feedback

DP83867CS Datasheet(PDF) 94 Page - Texas Instruments

DP83867CS Datasheet(HTML) 94 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL