DP83867CS datasheet(74/114 Pages) TI1

74 / 114 page

DP83867CS, DP83867IS, DP83867E

SNLS504 – OCTOBER 2015

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9.6.24 LED Configuration Register (LEDCR3)

This register controls the LED blink rate and stretching.

Table 35. LED Configuration Register 3 (LEDCR3), Address 0x001A

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:3

RESERVED

0, RO

RESERVED: Writes ignored, read as 0.

LEDS_BYPASS_STRETCHING

0, RW

Bypass LED Stretching:

1 = Bypass LED Stretching

0 = Normal operation

1:0

LEDS_BLINK_RATE

10, RW

LED Blink Rate:

11: 2Hz (500mSec)

10: 5Hz (200mSec)

01: 10Hz (100mSec)

00 = 20Hz (50mSec)

9.6.25 Configuration Register 3 (CFG3)

Table 36. Configuration Register 3 (CFG3), Address 0x001E

BIT

BIT NAME

DEFAULT

DESCRIPTION

Fast Link-Up in Parallel Detect

0, RW

Fast Link-Up in Parallel Detect Mode:

1 = Enable Fast Link-Up time During Parallel Detection

0 = Normal Parallel Detection link establishment

In Fast Auto MDI-X this bit is automatically set.

Fast AN Enable

0, RW

Fast Auto-Negotiation Enable:

1 = Enable Fast Auto-Negotiation mode – The PHY auto-

negotiates using Timer setting according to Fast AN Sel bits

0 = Disable Fast Auto-Negotiation mode – The PHY auto-

negotiates using normal Timer setting

Adjusting these bits reduces the time it takes to Auto-negotiate

between two PHYs. Note: When using this option care must be

taken to maintain proper operation of the system. While shortening

these timer intervals may not cause problems in normal operation,

there are certain situations where this may lead to problems.

13:12

Fast AN Sel

0, RW

Fast Auto-Negotiation Select bits:

Fast AN

Break

Link Fall

Auto-Neg

Select

Link

Inhibit

Wait

Timer(ms)

<00>

<01>

120

<10>

240

150

100

<11>

Adjusting these bits reduces the time it takes to Auto-negotiate

between two PHYs. In Fast AN mode, both PHYs should be

configured to the same configuration. These 2 bits define the

duration for each state of the Auto Negotiation process according

to the table above. The new duration time must be enabled by

setting “Fast AN En” - bit 4 of this register. Note: Using this mode

in cases where both link partners are not configured to the same

Fast Auto-negotiation configuration might produce scenarios with

unexpected behavior.

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