MSP430F435IPZ datasheet(33/85 Pages) TI

33 / 85 page

MSP430x43x, MSP430x44x

MIXED SIGNAL MICROCONTROLLER

SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

watchdog timer

The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a

software upset has occurred. A system reset is generated if the selected time interval expires. If an application

does not require this watchdog function, the module can work as an interval timer, which generates an interrupt

after a selected time interval.

The watchdog timer counter (WDTCNT) is a 15/16-bit up-counter not directly accessible by software. The

WDTCNT is controlled using the watchdog timer control register (WDTCTL), which is an 8-bit read/write register.

Writing to WDTCTL in either operating mode (watchdog or timer) is only possible when using the correct

password (05Ah) in the high byte. If any value other than 05Ah is written to the high-byte of the WDTCTL, a

system reset PUC is generated. The password is read as 069h to minimize accidental write operations to the

WDTCTL register. The low byte stores data written to the WDTCTL. In addition to the watchdog timer control

bits, there are two bits included in the WDTCTL that configure the NMI pin.

USART0 and USART1

There are two USART peripherals implemented in the MSP430x44x: USART0 and USART1; but only one in

the MSP430x43x configuration: USART0. Both have an identical function as described in the applicable

chapters of the MSP430x4xx User’s Guide. They use different pins to communicate, and different registers for

module control. Registers with identical functions have different addresses.

The universal synchronous/asynchronous interface is a dedicated peripheral module used in serial

communications. The USART supports synchronous SPI (3- or 4-pin), and asynchronous UART

communication protocols, using double-buffered transmit and receive channels. Data streams of 7 or 8 bits in

length can be transferred at a rate determined by the program, or by an external clock. Low-power applications

are optimized by UART mode options which allow for the reception of only the first byte of a complete frame.

The application software should then decide if the succeeding data is to be processed. This option reduces

power consumption.

Two dedicated interrupt vectors are assigned to each USART module—one for the receive and one for the

transmit channels.

timer_A (three capture/compare registers)

The timer module offers one 16-bit counter and three capture/compare registers. The timer clock source can

be selected from the external source TACLK (noninverted via SSEL=0 or inverted via SSEL=3), or from two

internal sources—ACLK (SSEL=1) or SMCLK (SSEL=2)). The clock source can be divided by one, two, four,

or eight. The timer can be fully controlled (in word mode)—it can be halted, read, and written. It can be stopped,

run continuously, or made to count up or up/down using one compare block to determine the period. The three

capture/compare blocks are configured by the application to run in capture or compare mode.

The capture mode is mostly used to individually measure internal or external events from any combination of

positive, negative, or positive and negative edges. It can also be stopped by software. Three different external

events (TA0, TA1, and TA2) can be selected. In the capture/compare register CCR2, ACLK is the capture signal

if CCI2B is selected. Software capture is chosen if CCISx=2 or CCISx=3.

The compare mode is mostly used to generate timing for the software or application hardware, or to generate

pulse-width modulated output signals for various purposes such as D/A conversion functions or motor control.

An individual output module is assigned to each of the three capture/compare registers. This module can run

independently of the compare function or can be triggered in several ways.

MSP430F435IPZ Datasheet(PDF) 33 Page - Texas Instruments

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