MSP430F435IPZ datasheet(64/85 Pages) TI

64 / 85 page

MSP430x43x, MSP430x44x

MIXED SIGNAL MICROCONTROLLER

SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

12-bit ADC, power supply and input range conditions (see Note 1) (continued)

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

(VeREF+ –

VREF–/VeREF–)

Differential external

reference voltage

input

VeREF+ > VeREF–/VeREF– (see Note 4)

1.4

V(AVCC)

VI(P6.x/Ax)

Analog input voltage

range (see Note 5)

All P6.0/A0 to P6.7/A7/SVSin terminals. Analog

inputs selected in ADC12MCTLx register and

P6Sel.x=1

≤ x ≤ 7; V(AVSS) ≤ VI(P6.x/Ax) ≤ V(AVCC)

V(AVCC)

IDD(ADC12)

Operating supply

current into AVCC

f(ADC12CLK) = 5 MHz

ADC12ON = 1, REFON = 0

VCC = 2.2 V

0.65

1.3

IDD(ADC12)

current into AVCC

terminal (see

Note 6)

ADC12ON = 1, REFON = 0

SHT0=0, SHT1=0,

ADC12DIV=0

VCC = 3 V

0.8

1.6

IDD(REF+)

Operating supply

current into AVCC

terminal (see

Note 7)

f(ADC12CLK) = 5 MHz

ADC12ON = 0,

REFON = 1, 2_5V = 1

VCC = 3 V

0.5

0.8

IDD(REF+)

Operating supply

f(ADC12CLK) = 5 MHz

ADC12ON

VCC = 2.2 V

0.5

0.8

O erating su

current (see Note 7)

()

ADC12ON = 0,

REFON = 1, 2_5V = 0

VCC = 3 V

0.5

0.8

NOTES:

5. The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results.

6. The internal reference supply current is not included in current consumption parameter IDD(ADC12).

7. The internal reference current is supplied via terminal AVCC. Consumption is independent of the ADC12ON control bit, unless a

conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.

12-bit ADC, built-in reference (see Note 1)

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

IDD(VeREF+)

Static input current

(see Note 2)

0 V

≤ VeREF+ ≤ V(AVCC)

VCC = 2.2 V/3 V

±1

µA

IDD(VREF–/VeREF–)

Static input current

(see Note 2)

0 V

≤ VeREF– ≤ V(AVCC)

VCC = 2.2 V/3 V

±1

µA

C(VREF+)

Capacitance at pin

VREF+ (see Note 3)

REFON = 1,

0 mA

≤ I(VREF+) ≤ I(VREF_max)

VCC = 2.2 V/3 V

µF

Ci‡

Input capacitance

(see Note 4)

Only one terminal can be selected

at one time, P6.x/Ax

VCC = 2.2 V

Zi‡

Input MUX ON

resistance (see Note 4)

0 V

≤ V(Ax) ≤ V(AVCC)

VCC = 3 V

2000

Ω

T(REF+)†

Temperature coefficient

of built-in reference

I(VREF+) is a constant in the range

of 0 mA

≤ I(VREF+) ≤ 1 mA

VCC = 2.2 V/3 V

±100 ppm/°C

† Not production tested, limits characterized

‡ Not production tested, limits verified by design

NOTES:

1. The voltage source on VeREF+ and VREF–/VeREF– needs to have low-dynamic impedance for 12-bit accuracy to allow the charge

to settle for this accuracy (See Figures 16 and 17).

2. The external reference is used during conversion to charge and discharge the capacitance array. The dynamic impedance should

follow the recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.

3. The internal buffer operational amplifier and the accuracy specifications require an external capacitor.

4. The input capacitance is also the dynamic load for an external reference during conversion. The dynamic impedance of the reference

supply should follow the recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy. All INL

and DNL tests uses two capacitors between pins VREF+ and AVSS and VREF–/VeREF– and AVSS: 10-µF tantalum and

100-nF ceramic.

MSP430F435IPZ Datasheet(PDF) 64 Page - Texas Instruments

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