MSP430F435IPZ datasheet(43/85 Pages) TI

43 / 85 page

MSP430x43x, MSP430x44x

MIXED SIGNAL MICROCONTROLLER

SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

control registers ADC12CTL0 and ADC12CTL1 (continued)

rw–(0) rw–(0) rw–(0) rw–(0)

01A2h

ADC12CTL1

rw–(0) rw–(0) rw–(0) r–(0)

rw–(0) rw–(0) rw–(0) rw–(0)

ADC12SSEL

ADC12DIV

CSStartAdd

rw–(0) rw–(0) rw–(0) rw–(0)

CONSEQ

SHS

ISSH

SHP

ADC12

BUSY

ADC12BUSY

01A2h, bit0

The BUSY signal indicates an active sample and conversion operation.

0: No conversion is active. The enable conversion bit ENC can be reset normally.

1: A sample period. Conversion or conversion sequence is active.

CONSEQ

01A2h, bit1/2

Select the conversion mode. Repeat mode is on if CONSEQ.1 (bit 1) is set.

0: One single channel is converted

1: One single sequence of channels is converted

2: Repeating conversion of one single channel

3: Repeating conversion of a sequence of channels

ADC12SSEL

01A2h, bit3/4

Selects the clock source for the converter core

0: Internal oscillator embedded in the ADC12 module

1: ACLK

2: MCLK

3: SMCLK

ADC12DIV

01A2h, bit5,6,7

Selects the division rate for the clock source selected by ADC12SSEL. The clock-operation

signal ADC12CLK is used in the converter core. The conversion, without sampling time,

requires 13 ADC12CLK clocks.

0 to 7: Divide the selected clock source by an integer from 1 to 8.

ISSH

01A2h, bit8

Invert source for the sample signal

0: The source for the sample signal is not inverted.

1: The source for the sample signal is inverted.

SHP

01A2h, bit9

Sample-and-hold pulse, programmable length of sample pulse

0: The sample operation lasts as long as the sample-and-hold signal is 1. The conversion

operation starts if the sample-and-hold signal goes from 1 to 0.

1: The sample time (sample signal is high) is defined by nx4x(1/fADC12CLK). SHTx holds

the data for n. The conversion starts when the sample signal goes from 1 to 0.

SHS

01A2h, bit10/11

Source for sample-and-hold

0: Control bit ADC12SC triggers sample-and-hold followed by the A/D conversion.

1: The trigger signal for sample-and-hold and conversion comes from Timer_A3.EQU1.

2: The trigger signal for sample-and-hold and conversion comes from Timer_B.EQU0.

3: The trigger signal for sample-and-hold and conversion comes from Timer_B.EQU1.

CStartAdd

01A2h, bit12 to

bit15

Conversion start address CstartAdd is used to define which ADC12 control memory is used

to start a (first) conversion. The value of CstartAdd ranges from 0 to 0Fh, corresponding

to ADC12MEM0 to ADC12MEM15 and the associated control registers ADC12MCTL0 to

ADC12MCTL15.

MSP430F435IPZ Datasheet(PDF) 43 Page - Texas Instruments

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