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MSP430F435IPZ Datasheet(PDF) 36 Page - Texas Instruments

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Part # MSP430F435IPZ
Description  MIXED SIGNAL MICROCONTROLLER
PDF  85 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

MSP430F435IPZ Datasheet(HTML) 36 Page - Texas Instruments

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MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
36
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
compare latches (TBCLx)
The compare latches can be loaded directly by software or via selected conditions triggered by the PWM
function and they are reset by the POR signal.
Load TBCLx immediate, CLLD=0:
Capture/compare register CCRx and the corresponding compare
latch are loaded simultaneously.
Load TBCLx at Zero, CLLD=1:
The data in capture/compare register CCRx is loaded to the
corresponding compare latch when the 16-bit timer TBR counts to
zero.
Load TBCLx at Zero + Period, CLLD=2:
The data in capture/compare register CCRx is loaded to the
corresponding compare latch when the 16-bit timer TBR counts to
zero or when the next period starts (in UP/DOWN mode).
Load TBCLx at EQUx, CLLD=3:
The data in capture/compare register CCRx is loaded when CCRx
is equal to TBR.
Loading the compare latches can be done individually or in groups. Individually means that whenever the
selected load condition (see above) is true, the CCRx data is loaded into TBCLx.
Load TBCLx individually, TBCLGRP=0:
Compare latch TBCLx is loaded when the selected load condition
(CLLD) is true.
Dual load TBCLx mode, TBCLGRP=1:
Two compare latches TBCLx are loaded when data are written to
both CCRx registers of the same group and the load condition
(CLLD) is true. Three groups are defined: CCR1+CCR2,
CCR3+CCR4, and CCR5+CCR6.
Triple load TBCLx mode, TBCLGRP=2:
Three compare latches TBCLx are loaded when data are written
to all CCRx registers of the same group and then the selected load
condition
(CLLD)
is
true.
Two
groups
are
defined:
CCR1+CCR2+CCR3 and CR4+CCR5+CCR6.
Full load TBCLx mode, TBCLGRP=3:
All seven compare latches TBCLx are loaded when data are
written to all seven CCRx registers and then the selected load
condition (CLLD) is true. All CCRx data, CCR0+CCR1+
CCR2+CCR3+CCR4+CCR5+CCR6, are simultaneously loaded
to the corresponding SHRx compare latches.



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