MSP430F435IPZ datasheet(14/85 Pages) TI

14 / 85 page

MSP430x43x, MSP430x44x

MIXED SIGNAL MICROCONTROLLER

SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

operating modes (continued)

D Low-power mode 3 (LPM3); SCG1=1, SCG0=1, OscOff=0, CPUOff=1:

–

CPU is disabled

MCLK, FLL+ loop control, and DCOCLK are disabled

DCO’s dc-generator is disabled

ACLK remains active

D Low-power mode 4 (LPM4); SCG1=X, SCG0=X, OscOff=1, CPUOff=1:

–

CPU is disabled

ACLK is disabled

MCLK, FLL+ loop control, and DCOCLK are disabled

DCO’s dc-generator is disabled

Crystal oscillator is stopped

SMCLK is disabled with SMCLKOFF bit in register FLL+CTL1 (054h). The selected clock source (DCOCLK or

XT2CLK) can be switched off only if SMCLKOFF = 1.

NOTE:

Peripheral operation is not halted by CPUOff. Peripherals are controlled by their individual control

registers.

The various operating modes are controlled by the software through control of the internal clock system

operation. This clock system gives a large combination of hardware and software capabilities to run the

application with the lowest power consumption and with optimized system costs:

D Use of the internal clock (DCO) generator without any external components

D Selection of an external crystal or ceramic resonator for lowest frequency and cost

D Application of an external clock source

The control bits that most influence the operation of the clock system and support fast turnon from low power

operating modes are located in the status register SR. Four bits control the CPU and the system clock generator:

SCG1, SCG0, OscOff, and CPUOff.

Reserved for Future

Enhancements

SCG1

SCG0

OscOff

CPUOff

GIE

rw–0rw–0rw–0rw–0rw–0rw–0rw–0rw–0rw–0rw–0

CPUOff, SCG1, SCG0, and OscOff are the most important bits in low-power control when the basic function

of the system clock generator is established. They are pushed to the stack whenever an interrupt is accepted

and saved for returning to the operation before an interrupt request. They can be manipulated via indirect access

to the data on the stack during execution of an interrupt handler so that program execution can resume in

another power operating mode after return-from-interrupt.

CPUOff:

The CPUOff bit, when set, disables CPU (MCLK is disabled).

SCG0:

The SCG0 bit, when set, disables the FLL+ loop control.

SCG1:

The SCG1 bit, when set, disables the DCOCLK signal.

OscOff:

The OscOff bit, when set, disables the LFXT1 crystal oscillator.

DC generator:

When both SCG0 and SCG1 are set, the dc generator for the DCO is disabled.

XT2Off:

The XT2Off bit, when set, disables the XT2 crystal oscillator. XT2 is disabled only if it is un-

used for MCLK (SELM

≠2 or CPUOff=1) and if it is unused for SMCLK (SELS=0 or

SMCLKOFF=1). Both conditions prevent disabling of XT2 accidentially.

SMCLKOFF:

SMCLKOFF, when set, switches off clock SMCLK.

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