MSP430F435IPZ datasheet(15/85 Pages) TI

15 / 85 page

MSP430x43x, MSP430x44x

MIXED SIGNAL MICROCONTROLLER

SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

interrupt vector addresses

The interrupt vectors and the power-up starting address are located in the address range 0FFFFh – 0FFE0h.

The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

Table 3. Interrupt Sources, Flags, and Vectors of 4xx Configurations

INTERRUPT SOURCE

INTERRUPT FLAG

SYSTEM INTERRUPT

WORD

ADDRESS

PRIORITY

Power-up

External Reset

Watchdog

Flash memory

WDTIFG

KEYV

(see Note 1)

Reset

0FFFEh

15, highest

NMI

Oscillator Fault

Flash memory access violation

NMIIFG (see Notes 1 and 3)

OFIFG (see Notes 1 and 3)

ACCVIFG (see Notes 1 and 3)

(Non)maskable

0FFFCh

Timer_B7†

CCIFG0 (see Note 2)

Maskable

0FFFAh

Timer_B7†

CCIFG1 to CCIFG6

TBIFG (see Notes 1 and 2)

Maskable

0FFF8h

Comparator_A

CAIFG

Maskable

0FFF6h

Watchdog Timer

WDTIFG

Maskable

0FFF4h

USART0 receive

URXIFG0

Maskable

0FFF2h

USART0 transmit

UTXIFG0

Maskable

0FFF0h

ADC

ADCIFG (see Notes 1 and 2)

Maskable

0FFEEh

Timer_A3

CCIFG0 (see Note 2)

Maskable

0FFECh

Timer_A3

CCIFG1, CCIFG2,

TAIFG (see Notes 1 and 2)

Maskable

0FFEAh

I/O port P1 (eight flags)

P1IFG.0 (see Notes 1 and 2)

P1IFG.7 (see Notes 1 and 2)

Maskable

0FFE8h

USART1 receive‡

URXIFG1

Maskable

0FFE6h

USART1 transmit‡

UTXIFG1

Maskable

0FFE4h

I/O port P2 (eight flags)

P2IFG.0 (see Notes 1 and 2)

P2IFG.7 (see Notes 1 and 2)

Maskable

0FFE2h

Basic Timer1

BTIFG

Maskable

0FFE0h

0, lowest

‡ ’43x uses Timer_B3 with CCIFG0, CCIFG1 to CCIFG2 flags, and TBIFG. ’44x uses Timer_B7 with CCIFG0, CCIFG1 to CCIFG6, and TBIFG

‡ USART1 is implemented in ’44x only.

NOTES:

1. Multiple source flags

2. Interrupt flags are located in the module.

3. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable can not disable

it.

special function registers

Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits

not allocated to a functional purpose are not physically present in the device. This arrangement provides simple

software access.

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