MSP430F435IPZ datasheet(44/85 Pages) TI

44 / 85 page

MSP430x43x, MSP430x44x

MIXED SIGNAL MICROCONTROLLER

SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

control register ADC12MCTLx and conversion memory ADC12MEMx

All control bits are reset during POR. POR is active after application of VCC, or after a reset condition is applied

to pin RST/NMI. Control registers ADC12MCTL.x can be modified only if enable conversion control bit ENC is

reset. Any instruction that writes to an ADC12MCTLx register while the ENC bit is reset has no effect. A more

detailed description of the control bit functions is found in the ADC12 module description (in the MSP430x3xx

User’s Guide).

There are 16 ADC12MCTLx 8-bit memory control registers and 16 ADC12MEMx 16-bit registers. Each of the

memory control registers is associated with one ADC12MEMx register; for example, ADC12MEM0 is

associated with ADC12MCTL0, ADC12MEM1 is associated with ADC12MCTL1, etc.

080h....08Fh

ADC12MCTLx

rw–(0)

INCH, Input Channel a0 to a11

Sref, Source of Reference

EOS

rw–(0)

The control register bits are used to select the analog channel, the reference voltage sources for VR+ and VR–,

and a control signal which marks the last channel in a group of channels. The sixteen 16-bit registers

ADC12MEMx are used to hold the conversion results.

The following illustration shows the conversion-result registers ADC12MEM0 to ADC12MEM15:

0140h...015Eh

ADC12MEM

rw–(0)

MSB

LSB

rw–(0) rw–(0) rw–(0) rw–(0) rw–(0) rw–(0) rw–(0) rw–(0) rw–(0) rw–(0) rw–(0)

ADC12MEM0

0140h, bit0,

The 12 bits of the conversion result are stored in 16 control registers

ADC12MEM0 to ADC12MEM15.

ADC12MEM15

015Eh, bit15

The 12 bits are right-justified and the upper four bits are always read as 0.

ADC12 interrupt flags ADC12IFG.x and enable registers ADC12IEN.x

There are 16 ADC12IFG.x interrupt flags, 16 ADC12IE.x interrupt-enable bits, and one interrupt-vector word.

The 16 interrupt flags and enable bits are associated with the 16 ADC12MEMx registers. For example, register

ADC12MEM0, interrupt flag ADC12IFG.0, and interrupt-enable bit ADC12IE.0 form one conversion-result

block.

ADC12IFG.0 has the highest priority and ADC12IFG.15 has the lowest priority.

All interrupt flags and interrupt-enable bits are reset during POR. POR is active after application of VCC or after

a reset condition is applied to the RST/NMI pin.

ADC12 interrupt vector register

The 12-bit ADC has one interrupt vector for the overflow flag, the timing overflow flag, and 16 interrupt flags.

This vector indicates that a conversion result is stored into registers ADC12MEMx. Handling of the 18 flags is

assisted by the interrupt-vector word. The 16-bit vector word ADC12IV indicates the highest pending interrupt.

The interrupt-vector word is used to add an offset to the program counter so that the interrupt-handler software

continues at the corresponding program location according to the interrupt event. This simplifies the interrupt-

handler operation and assigns each interrupt event the same 5-cycle overhead.

MSP430F435IPZ Datasheet(PDF) 44 Page - Texas Instruments

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