MSP430F435IPZ datasheet(30/85 Pages) TI

30 / 85 page

MSP430x43x, MSP430x44x

MIXED SIGNAL MICROCONTROLLER

SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

digital I/O (continued)

The seven control registers are:

D Input register

8 bits at ports P1 through P6

D Output register

8 bits at ports P1 through P6

D Direction register

8 bits at ports P1 through P6

D Interrupt edge select

8 bits at ports P1 and P2

D Interrupt flags

8 bits at ports P1 and P2

D Interrupt enable

8 bits at ports P1 and P2

D Selection (port or module)

8 bits at ports P1 through P6

Each of these registers contains eight bits. Two interrupt vectors are implemented: one commonly used for any

interrupt event on ports P1.0 to P1.7, and another commonly used for any interrupt event on ports P2.0 to P2.7.

Ports P3, P4, P5, and P6 have no interrupt capability.

Basic Timer1

The Basic Timer1 (BT1) divides the frequency of SMCLK or ACLK, as selected with the SSEL bit, to provide

low-frequency control signals. This is done within the system by one central divider, the Basic Timer1, to support

low-current applications. The BTCTL control register contains the flags that control or select the different

operational functions. When the supply voltage is applied or when a device is reset (RST/NMI pin), a watchdog

overflow or a watchdog security key violation occurs; all bits in the register hold undefined or unchanged status.

The user software usually configures the operational conditions on the BT during initialization. The Basic Timer1

has two eight-bit timers which can be cascaded to a sixteen-bit timer. Both timers can be read and written by

software. Two bits in the SFR address range handle the system control interaction according to the function

implemented in the Basic Timer1. These two bits are the Basic Timer1 interrupt flag (BTIFG) and the Basic

Timer1 interrupt enable (BTIE) bit.

LCD drive

The liquid crystal displays (LCDs) for static, 2-MUX, 3-MUX, and 4-MUX operation can be driven directly. The

operation of the controller LCD logic is defined by software through memory-bit manipulation. The LCD memory

is part of the LCD module, not part of data memory. Eight mode and control bits define the operation and current

consumption of the LCD drive. The information for the individual digits can be easily obtained using table

programming techniques combined with the proper addressing mode. The segment information is stored into

LCD memory using instructions for memory manipulation.

The drive capability is defined by the external resistor divider that supports analog levels for 2-, 3-, and 4-MUX

operation. Groups of the digital I/O-LCD segment lines can be selected to have either digital I/O or LCD function.

Digital I/Os are selected by default after POR and PUC. The LCD provides four common lines and four terminals

for adjusting the analog levels. The configuration for MSP430x44x and MSP430x43x with 100 pins has

40 segment lines and the configuration for MSP430x43x with 80 pins has 32 segment lines.

MSP430F435IPZ Datasheet(PDF) 30 Page - Texas Instruments

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