MSP430F435IPZ datasheet(35/85 Pages) TI

35 / 85 page

MSP430x43x, MSP430x44x

MIXED SIGNAL MICROCONTROLLER

SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

timer_B (7 capture/compare registers in ’x44x and three capture/compare registers in ’x43x)

Timer_B7 is identical to Timer_A3, except for the following:

D The timer counter can be configured to operate in 8-, 10-, 12-, or 16-bit mode.

D The function of the capture/compare registers is slightly different when in compare mode. In Timer_B, the

compare data is written to the capture/compare register, but is then transferred to the associated compare

latch for the comparison.

D All output level Outx can be set to Hi-Z from the TboutH external signal.

D The SCCI bit is not implemented in Timer_B

D Timer_B7 has seven capture compare registers

The timer module has one 16-bit counter and seven capture/compare registers. The timer clock source can be

selected from an external source TBCLK (SSEL=0) or TBCLK (SSEL=3), or from two internal sources: ACLK

(SSEL=1) and SMCLK (SSEL=2)). The clock source can be divided by one, two, four, or eight. The timer can

be fully controlled (in word mode): it can be halted, read, and written; it can be stopped, run continuously, or

made to count up or up/down using one compare block to determine the period. The seven capture/compare

blocks are configured by the application to run in capture or in compare mode.

The capture mode is mostly used to measure external or internal events from any combination of positive,

negative, or positive and negative edges. It can also be stopped by software. Any of seven different external

events TB0 to TB6 can be selected. In the capture/compare register CCR6, ACLK is the capture signal if CCI6B

is selected. Software capture is chosen if CCISx=2 or CCISx=3.

The compare mode is mostly used to generate timing for the software or application hardware, or to generate

pulse-width modulated output signals for various purposes such as D/A conversion functions or motor control.

An individual output module is assigned to each of the seven capture/compare registers. This module can run

independently of the compare function, or can be triggered in several ways. The comparison is made from the

data in the compare latches (TBCLx) and not from the compare register.

Two interrupt vectors are used by the module. One vector is assigned to capture/compare block CCR0, and one

common interrupt vector is implemented for the timer and the other six capture/compare blocks. The seven

interrupt events using the same vector are identified by an individual interrupt vector word. The interrupt vector

word is used to add an offset to the program counter so that the interrupt handler software continues at the

corresponding program location. This simplifies the interrupt handler and assigns each interrupt event the same

5-cycle overhead.

MSP430F435IPZ Datasheet(PDF) 35 Page - Texas Instruments