STA400A datasheet(12/117 Pages) STMICROELECTRONICS

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STA400A

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IF AGC

To maintain constant the signal levels at the A/D converters input, two 1-bit Pulse Density Modulated (PDM)

signals (SAGC for satellite and TAGC for terrestrial branch) are generated to drive an external IF AGC.

The difference between the user programmable reference level and the power of the input samples is integrated

by the programmable gain loop filter and then sent to a 1-bit modulator to generate the output control signal.

The sense of this signal is programmable to adapt it to a positive or negative slope of the variable gain amplifier.

The SAGC and TAGC outputs can be filtered by an external low pass filter to close the AGC loop (see fig.3); in

this way the mean power of the ADCs input signal is forced to the reference.

The AGC loop gain is given by:

βAGC = 2xAGCBETA. The parameter xAGCBETA can take values from 0 to 6.

When xAGCBETA="111" the loop gain is zero. The AGC loop may be opened by programming "111" in the x

AGCBETA parameter and writing "00000000" in the xAGCINTG register. In this condition the control signal is a

50% duty-cycle square wave with a frequency of MCLK/2 (23.92MHz/2=11.96MHz).

The 8 MSBs of the integrator register may be read at any time in the xAGCINTG register. This value is the level

of the AGC outputs after low pass filtering; it gives an image of the input signal power at the terrestrial and sat-

ellite branch respectively.

The reference level can be set by the xAGCREF register, the loop gain and the sense of the control pins (TAGC

and SAGC) are set by the AGC_CTRL1 register described in section 2.6.

CONTROL Registers

The IF_CTRL, CONTROL and STATUS1 are the control registers of the IF Sampling interface (see section 2.6).

To have a more stable reading of the xAGCINTG register a moving average filter over 2048 samples is used.

This filter can be enabled or disabled by the bit7 of the IF_CTRL register.

The data bit from the external ADCs (if used) may have a two's complement or offset binary format. Bit1 of the

IF_CTRL register sets the binary format for the digital IF inputs.

The CONTROL register configures the master clock outputs (MCLKO and MCLKON) and the external memory

mode access of the bi-directional bus (MDQ[7:0]). When the master clock output buffers are disabled the output

levels are fixed to ground resulting in no activity on these pins; this aproach minimizes the interferences when

these signals are not used.

The bi-directional buffers of the STA400A and the input/output mask of the external SDRAM are controlled by

the MDQM pin. The STA400A has a low level active bi-directional buffers (high level on the enable drives the

buffers to Hi-Z). The input/output mask operation of the external SDRAM may be selected active HIGH or active

LOW (see figure 5) setting the MDQM_CTRL parameter of the CONTROL register (bit5).

Figure 5. Input/Output Mask Configuration

MDQM_CTRL

DATA

OUTPUT

MDQ[7:0]

MDQM

STA400

SDRAM

MDQ

BIDIR

BUFFER

MDQM

OUTPUT

BUFFER

DATA

INPUT

I/O MASK

STA400A

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