STA400A datasheet(42/117 Pages) STMICROELECTRONICS

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STA400A

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2.2 QPSK Demodulator (S1-Early/S2-Late)

The two QPSK demodulators (S1-Early and S2-Late) have the same register set so they have been listed below

once. The registers have different addresses and the same reset value except for the IFFREQ register.

QPSK_DEMOD_EN - QPSK Demodulator Enable Register

This register disables the QPSK demodulator when bit-0 is set to '0'. When disabled the demodulator output is

fixed to '0x00' or to '0x80' depending on the bit-4 setting of the QPSK_CTRL register (address 0x005A/0x0080)

b7-b1:

Not Used

b0:

DEM_EN

0=Demodulator disabled; 1=Demodulator enabled.

QPSK_CTRL - QPSK Demodulator Control Register

This is a control register for the QPSK demodulator.

b7:

AVG_OFF

This bit disables the averager filter of the integrators.

0=Averager Filter enabled; 1=Averager Filter disabled.

b6:

NULOFS_EN

This bit enables/disables the NULOFS block.

0=Disabled; 1=Enabled.

b5:

Reserved.

b4:

DEM2TDM_FMT

Output Data Format.

0=Two's complement; 1=Offset binary.

b3:

IQSWAP

This bit swaps the I and Q component of the demodulator output.

0=No Change; 1=Swaps I with Q.

b2:

QCHS

This bit inverts the Q component sign in the I/Q mixer.

0=No invertion; 1=Sign invertion.

b1:

TIMCHS

This bit inverts the timing loop sign.

0=No invertion; 1=Sign invertion.

b0:

CARCHS

This bit inverts the carrier loop sign.

0=No invertion; 1=Sign invertion.

Type:

SingleByte - R/W

Word Length:

Byte Name

Address (Hex)

Bit Map

Reset Value (Hex)

QPSK_DEMOD_EN1

S1/S2

0059/007F

7-0

Type:

SingleByte - R/W

Word Length:

Byte Name

Address (Hex)

Bit Map

Reset Value (Hex)

QPSK_CTRL

S1/S2

005A/0080

7-0

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