MSP4458 datasheet(16/85 Pages) MICRONAS

16 / 85 page

MSP 44x8G

PRELIMINARY DATA SHEET

Micronas

3.1.2. Description of CONTROL Register

3.1.3. Protocol Description

Write to DSP or Demodulator

Read from DSP or Demodulator

Write to Control or Test Registers

Note: S =

I2C-Bus Start Condition from master

P =

I2C-Bus Stop Condition from master

ACK = Acknowledge-Bit: LOW on I2C_DA from slave (= MSP, light gray) or master (= controller, dark gray)

NAK = Not Acknowledge-Bit: HIGH on I2C_DA from master (dark gray) to indicate ‘End of Read’

or from MSP indicating internal error state

Wait = I2C-Clock line is held low, while the MSP is processing the I2C command.

Fig. 3–1: I2C bus protocol (MSB first; data must be stable while clock is high)

Table 3–3: CONTROL as a Write Register

Name

Subaddress

Bit[15] (MSB)

Bits[14:0]

CONTROL

00hex

1 : RESET

0 : normal

Table 3–4: CONTROL as a Read Register

Name

Subaddress

Bit[15] (MSB)

Bit[14]

Bits[13:0]

CONTROL

00hex

Reset status after last reading of CONTROL:

0 : no reset occured

1 : reset occured

Internal hardware status:

0 : no error occured

1 : internal error occured

not of interest

Reading of CONTROL will reset the bits[15,14] of CONTROL. After Power-on,

bit[15] of CONTROL will be set; it must be

read once to be reset.

Swrite

device

address

Wait

ACK sub-addr ACK addr-byte

high

ACK addr-byte

low

ACK data-byte-

high

ACK data-byte

low

ACK

Swrite

device

address

Wait

ACK sub-addr ACK addr-byte

high

ACK addr-byte

low

ACK

read

device

address

Wait

ACK data-byte-

high

ACK data-byte

low

NAK

Swrite

device

address

Wait

ACK sub-addr ACK data-byte

high

ACK data-byte

low

ACK

I2C_DA

I2C_CL

MSP4458 Datasheet(PDF) 16 Page - Micronas

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