MT9072AB datasheet(131/275 Pages) ZARLINK

131 / 275 page

MT9072

Data Sheet

131

Zarlink Semiconductor Inc.

Bit

Name

Functional Description

15-12

not used.

RXclk

This bit represents the receiver clock generated after the RXEN control bit, but before

zero deletion is considered.

TXclk

This bit represents the transmit clock generated after the TXEN control bit, but before zero

insertion is considered.

Vcrc

This is the CRC recognition status bit for the receiver. Data is clocked into the register and

then this bit is monitored to see if comparison was successful (bit will be high).

Vaddr

This is the address recognition status bit for the receiver. Data is clocked into the Address

Recognition Register and then this bit is monitored to see if comparison was successful

(bit will be high).

7-0

TBP7-0

Transmit Byte Counter Position. These 7 bits provide the position of the Transmit HDLC

Byte Counter register (YF6). The counter is decremented as a byte of data is sent through

the Transmit FIFO.

When this register reaches the count of one, the next write to the Tx FIFO will be tagged

as an end of packet byte. The counter decrements at the end of the write to the Tx FIFO.

If the Cycle bit of YF2 is set high, the counter will cycle through the programmed value

continuously.

Table 91 - Transmit Byte Counter Position and HDLC Test Status(Y1C) (T1)

Bit

Name

Functional Description

15-7

not used.

6IDC

Idle Channel State.Is set to a 1 when an idle Channel state (15 or more ones) has been

detected at the receiver. This is an asynchronous event. On power reset, this may be 1 if

the clock (RXC) was not operating. Status becomes valid after the first 15 bits or the first

zero is received.

5-4

RQ9-8

RQ9-8Byte Status bits from RX FIFO. These bits determine the status of the byte to be

read from RX FIFO as follows:

00 Packet Byte

01 First Byte

10 Last byte of good packet

11 Last byte of bad packet

3-2

TXSTAT1-0 Transmit FiFO Status:

00 Transmit FIFO is full.

01 The number of bytes in the transmit FIFO has reached or exceeded the 16 bytes

threshold

10 Transmit FIFO is empty

11 The number of bytes in the TX FIFO is less than the 16 byte threshold.

1-0

RXSTAT1-0 Receive FiFO Status:

00 Receive FIFO is empty.

01 The number of bytes in the Receive FIFO are less than the 16 bytes

10 Receive FIFO is full

11 The number of bytes in the Receive FIFO is greater than or equal to the 16 byte

threshold.

Table 92 - HDLC Status Word(Y1D) (T1)

MT9072AB Datasheet(PDF) 131 Page - Zarlink Semiconductor Inc

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