MT9072AB datasheet(134/275 Pages) ZARLINK

134 / 275 page

MT9072

Data Sheet

134

Zarlink Semiconductor Inc.

Bit

Name

Functional Description

FEOL

Framing Bit Error Counter Overflow Latch. This bit is set when the framing bit

counter(Y17) overflows. This bit is cleared after a read of Y24 or Y34.

CRCOL

CRC-6 Error Counter Overflow Latch. This bit is set if the CRC6 error counter(Y19)

overflows. This bit is cleared after a read of Y24 or Y34.

OOFOL

Out Of Frame Counter Overflow Latch. This bit is set when the OOF counter(Y1A)

overflows. This bit is cleared after a read of Y24 or Y34.

COFAOL

Change of Frame Alignment Counter Overflow Latch. This bit is set when the change

of frame alignment counter (Y1A) overflows. This bit is cleared after a read of Y24 or Y34.

BPVOL

Bipolar Violation Counter Overflow Latch. This bit is set when the bipolar violation

counter(Y18) overflows.This bit is cleared after a read of Y24 or Y34.

PRBSOL

Pseudo Random Bit Sequence Error Counter Overflow Latch. This bit is set when the

PRBS error counter(Y15) overflows. This bit is cleared after a read of Y24 or Y34.

PRBSMFOL PRBS Multiframe Counter Overflow Latch. This bit is set when the PRBS multiframe

counter(Y15) overflows. This bit is cleared after a read of Y24 or Y34.

MFOOFOL Multiframe Out of Frame Counter Overflow Latch. This bit is set if the Multiframe Out of

Frame Counter(Y16) overflows. This bit is cleared after a read of Y24 or Y34.

TFSYNL

Terminal Out Of Sync Latch. This bit is set when the terminal frame out of sync condition

is acquired or lost. It is the latched version of the TFSYNC bit(Y10). This bit is cleared after

a read of Y24 or Y34.

MFSYNL

Multiframes Out Of Sync Latch. This bit is set when the multiframes out of sync condition

is acquired or lost. It is the latched version of the MFSYNC bit (Y10).This bit is cleared after

a read of Y24 or Y34.

FBEL

Framing Bit Error Latch. This bit is set when a framing bit error is detected. It is cleared

upon a read. It is the latched version of the Framing Bit Counter (Y17) event. This bit is

cleared after a read of Y24 or Y34.

4COFAL

Change of Frame Alignment Latch. This bit is set when the change of frame alignment

occurs. This is the latched version of the count event to change of frame counter (Y1A).

This bit is cleared after a read of Y24 or Y34.

SEFL

Severely Errored Frame Latch. This bit is set upon receipt of a line loopback disable

code. This is a latched version of Y10. This bit is cleared after a read of Y24 or Y34.

2AISL

AIS Latch. This bit is set upon receipt of an AIS. This is a latched version of AIS(Y10).This

bit is cleared after a read of Y24 or Y34.

CRCL

CRC Error Latched. This bit is set when the receive CRC error occurs. This bit is cleared

after a read of Y24 or Y34.

0LOSL

Digital Loss of Signal. This bit goes high after the detection of 192 or 32 consecutive

zeros. This is the latched version of LOS(Y10). This bit is cleared after a read of Y24 or

Y34.

Table 96 - Receive Sync and Alarm Latch(Y24) (T1)

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