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MT9072AB Datasheet(PDF) 132 Page - Zarlink Semiconductor Inc

Part # MT9072AB
Description  Octal T1/E1/J1 Framer
PDF  275 Pages
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Manufacturer  ZARLINK [Zarlink Semiconductor Inc]
Direct Link  http://www.zarlink.com
Logo ZARLINK - Zarlink Semiconductor Inc

MT9072AB Datasheet(HTML) 132 Page - Zarlink Semiconductor Inc

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MT9072
Data Sheet
132
Zarlink Semiconductor Inc.
17.1.5
Latched Status Registers (Y20 - Y2F) Bit Functions
Tables 96 and 103 describe the bit functions of each of the Latched Status Registers in the MT9072 for T1. Each
register is repeated for each of the 8 framers. Framer 0 is addressed with Y=0, Framer 1 with Y=1, Framer 2 with
Y=2 ... and Framer 7 with Y=7 (where Y represents the 4 most significant address bits (MSB) A11,A10 A9 A8). All
latched status registers will be reset in the inactive state upon reset.
Bit
Name
Functional Description
15-0
RCRC15-0 Received CRC. This register contains the CRC received from the transmitter. These bits
are as the transmitter sent them, the LSB of the FCS sequence is MSB in this register. This
register is updated at the end of each received packet and therefore should be read when
end of packet is detected.
Table 93 - HDLC Receive CRC(Y1E) (T1)
Bit
Name
Functional Description
7-0
RXFIFO7-0 Receive FIFO.This is the received data byte read from the RX FIFO. The status bits of
this byte can be read from the status register. The FIFO status is not changed
immediately when a write or read occurs. It is updated after the data has settled and the
transfer to the last available position has finished.
Note that if the HDLC receiver is connected to an receive T1 channel, the bit that arrived
first is stored in the least significant bit of the receive FIFO.
Table 94 - Receive FIFO(Y1F) (T1)



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