MT9072AB datasheet(176/275 Pages) ZARLINK

176 / 275 page

MT9072

Data Sheet

176

Zarlink Semiconductor Inc.

Bit

Name

Functional Description

15-7

not used.

6ELAS

(0)

Elastic Buffer Enable. When this bit is set to one, the data at DSTo is a 2.048 Mb/s serial output

stream which contains all 32 timeslots of the received PCM30 link data after HDB3 decoding.

This data does not pass through the elastic buffer and is clocked out with the falling edge of

EXCLi. The data at the DSTo pin is identical to the data at the RXDL pin. When this bit is set to

zero, the elastic buffer is enabled, and DSTo operates synchronously with the clock at the CKi

pin.

Note that only RXDLC or the EXCL can be used to clock DSTo data and DSTo data has no

relationship to CKi when ELAS is1.

5ACCLR

(0)

Automatic Counter Clear. When this bit is set to one, all non-latched status counters (address

Y15 to Y1A) are cleared automatically by the one second timer bit ONESEC (address Y11)

immediately following the counter latch operation (address Y25 to Y2B). If zero, all non-latched

status counters operate normally.

4RxTRS

(0)

Receive Transparent Mode. If one, the framing function is disabled on the receive side. Data

coming from the receive line passes through the slip buffer and drives DSTo with an arbitrary

alignment. When zero, the receive framing function operates normally.

3TxTRS

(0)

Transmit Transparent Mode. If one, the MT9072 is in transmit transparent mode where no

framing or signaling is imposed on data transmitted from DSTi onto the PCM30 line. In other

words, timeslot 0 and timeslot 16 data on the transmit PCM30 link is sourced from the DSTi

input. If zero, the MT9072 is in termination mode.

2CSIG

(0)

CCS and CAS signaling. If one, the MT9072 is in Common Channel signaling (CCS) mode. If

zero, the MT9072 is in Channel Associated signaling (CAS) mode.

CNCLR

(0)

Counter Clear. When this bit is changed from zero to one, all non-latched status counters

(address Y15 to Y1A) are cleared. If zero, all non-latched status counters operate normally.

0RST

(0)

Reset. When this bit is changed from zero to one, the selected framer (Y) will reset to its default

mode. See the Reset Operation section for the default settings.

Table 145 - DL, CCS, CAS and Other Control Register (R/W Address Y03) (E1)

Bit

Name

Functional Description

15-2

not used.

1-0

SIP1-0 Signaling Interrupt Period. These 2 bits determine the signaling Interrupt period due to the

Receive signaling changes. This 2 bits determine the duration of the signaling interrupt bit

CASRI(Y36).

00 2 msec Period

01 8 msec Period

10 16 msec Period

Table 146 - Signaling Period Interrupt Word (R/W Address Y04) (E1)

MT9072AB Datasheet(PDF) 176 Page - Zarlink Semiconductor Inc

MT9072AB Datasheet(HTML) 176 Page - Zarlink Semiconductor Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL